Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver 74HCT125 PDIP 14

SN54HCT125, SN74HCT125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCLS069E – NOVEMBER 1988 – REVISED AUGUST 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Operating Voltage Range of 4.5 V to 5.5 V

High-Current Outputs Drive Up To 15

LSTTL Loads

Low Power Consumption, 80-µA Max I

Typical t

= 12 ns

±6-mA Output Drive at 5 V

Low Input Current of 1 µA Max

Inputs Are TTL-Voltage Compatible

High-Current 3-State Outputs Drive Bus

Lines or Buffer Memory Address Registers

SN54HCT125 ...J OR W PACKAGE

SN74HCT125 ...D OR N PACKAGE

(TOP VIEW)

3212019

910111213

3OE

2OE

1OE

4OE

GND

SN54HCT125 . . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

1OE

2OE

GND

4OE

3OE

description/ordering information

These bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the

associated output-enable (OE

) input is high.

To ensure the high-impedance state during power up or power down, OE

should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

–40 C to 85 C

PDIP – N Tube of 25 SN74HCT125N SN74HCT125N

–40°C to 85°C

SOIC – D

Tube of 50 SN74HCT125D

HCT125

–40°C to 85°C

SOIC – D

Reel of 2500 SN74HCT125DR

HCT125

Reel of 250 SN74HCT125DT

–55 C to 125 C

CDIP – J Tube of 25 SNJ54HCT125J SNJ54HCT125J

–55

C to 125

CFP – W Tube of 150 SNJ54HCT125W SNJ54HCT125W

LCCC – FK Tube of 55 SNJ54HCT125FK SNJ54HCT125FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (12 pages)

PAGE 1
SN54HCT125, SN74HCT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS069E – NOVEMBER 1988 – REVISED AUGUST 2003 D D D D Operating Voltage Range of 4.5 V to 5.5 V High-Current Outputs Drive Up To 15 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 12 ns D D D D ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible High-Current 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers SN54HCT125 . . .
PAGE 2
SN54HCT125, SN74HCT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS069E – NOVEMBER 1988 – REVISED AUGUST 2003 FUNCTION TABLE (each gate) INPUTS OE A OUTPUT Y L H H L L L H X Z logic diagram (positive logic) OE A Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
PAGE 3
SN54HCT125, SN74HCT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS069E – NOVEMBER 1988 – REVISED AUGUST 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH VI = VIH or VIL IOH = –20 µA IOH = –6 mA 4.5 V VOL VI = VIH or VIL IOL = 20 µA IOL = 6 mA 4.5 V II IOZ VI = VCC or 0 VO = VCC or 0, ICC VI = VCC or 0, One input at 0.5 V or 2.
PAGE 4
SN54HCT125, SN74HCT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS069E – NOVEMBER 1988 – REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION VCC PARAMETER tPZH ten S1 From Output Under Test CL (see Note A) 1 kΩ tPZL RL tPHZ tdis CL S1 S2 50 pF or 150 pF Open Closed Closed Open Open Closed Closed Open Open Open RL 1 kΩ 50 pF tPLZ S2 tpd or tt –– 50 pF or 150 pF LOAD CIRCUIT 3V 1.3 V Input 1.3 V 0V tPZL 3V Input 1.3 V 1.3 V 0V tPLH Output 1.
PAGE 5
PACKAGE OPTION ADDENDUM www.ti.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 to Customer on an annual basis.
PAGE 7
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HCT125DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HCT125DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HCT125DR SOIC D 14 2500 367.0 367.0 38.0 SN74HCT125DT SOIC D 14 250 367.0 367.0 38.
PAGE 9
PAGE 10
PAGE 11
PAGE 12
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.