Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver SOIC 20

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SCLS174E − MARCH 1984 − REVISED AUGUST 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Operating Voltage Range of 4.5 V to 5.5 V

D High-Current Outputs Drive Up To 15

LSTTL Loads

D Low Power Consumption, 80-µA Max I

D Typical t

= 12 ns

D ±6-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

D Inputs Are TTL-Voltage Compatible

D 3-State Outputs Drive Bus Lines or Buffer

Memory Address Registers

description/ordering information

These octal buffers and line drivers are designed

specifically to improve both the performance and

density of 3-state memory address drivers, clock

drivers, and bus-oriented receivers and

transmitters. The ’HCT240 devices are organized

as two 4-bit buffers/drivers with separate

output-enable (OE

) inputs. When OE is low, the

device passes inverted data from the A inputs to

the Y outputs. When OE

is high, the outputs are

in the high-impedance state.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 20 SN74HCT240N SN74HCT240N

SOIC − DW

Tube of 25 SN74HCT240DW

HCT240

SOIC − DW

Reel of 2000 SN74HCT240DWR

HCT240

−40°C to 85°C

SOP − NS Reel of 2000 SN74HCT240NSR HCT240

−40 C to 85 C

Tube of 70 SN74HCT240PW

TSSOP − PW

Reel of 2000 SN74HCT240PWR

HT240

TSSOP − PW

Reel of 250 SN74HCT240PWT

HT240

CDIP − J Tube of 20 SNJ54HCT240J SNJ54HCT240J

−55°C to 125°C

CFP − W Tube of 85 SNJ54HCT240W SNJ54HCT240W

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54HCT240FK SNJ54HCT240FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

1OE

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

GND

2OE

1Y1

2A4

1Y2

2A3

1Y3

2A2

1Y4

2A1

SN54HCT240 ...J OR W PACKAGE

SN74HCT240 ...DW, N, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

1Y1

2A4

1Y2

2A3

1Y3

1A2

2Y3

1A3

2Y2

1A4

SN54HCT240...FK PACKAGE

(TOP VIEW)

2Y4

1A1

1OE

1Y4

2A2 2OE

2Y1

2A1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (19 pages)

PAGE 1
SCLS174E − MARCH 1984 − REVISED AUGUST 2003 D D D D D D LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 12 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers SN54HCT240 . . . J OR W PACKAGE SN74HCT240 . . .
PAGE 2
SCLS174E − MARCH 1984 − REVISED AUGUST 2003 FUNCTION TABLE (each buffer/driver) INPUTS OE A OUTPUT Y L H L L L H H X Z logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 1 2OE 2 4 18 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 19 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . .
PAGE 3
SCLS174E − MARCH 1984 − REVISED AUGUST 2003 recommended operating conditions (see Note 3) SN54HCT240 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO ∆t/∆v Output voltage 0 High-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V SN74HCT240 2 2 Input transition rise/fall time V V 0.8 VCC VCC UNIT 0 0 500 0.
PAGE 4
SCLS174E − MARCH 1984 − REVISED AUGUST 2003 switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpd A Y ten OE Y tt Y VCC MIN TA = 25°C TYP MAX SN54HCT240 MIN MAX SN74HCT240 MIN MAX 4.5 V 20 42 63 53 5.5 V 19 38 56 48 4.5 V 25 52 79 65 5.5 V 22 47 71 59 4.5 V 17 42 63 53 5.
PAGE 5
SCLS174E − MARCH 1984 − REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test CL (see Note A) PARAMETER S1 Test Point tPZH ten RL S2 1 kΩ tPZL tPHZ tdis S2 50 pF or 150 pF Open Closed Closed Open Open Closed Closed Open Open Open 50 pF tPLZ −− LOAD CIRCUIT 2.7 V S1 1 kΩ tpd or tt Input 1.3 V 0.3 V CL RL 2.7 V 50 pF or 150 pF 3V 1.3 V 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74HCT240DWR Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) DW 20 2000 330.0 24.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.8 13.0 2.7 12.0 24.0 Q1 SN74HCT240NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1 SN74HCT240PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HCT240DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74HCT240NSR SO NS 20 2000 367.0 367.0 45.0 SN74HCT240PWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74HCT240PWT TSSOP PW 20 250 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.