Datasheet

1
2
4
6
8
19
11
13
15
17
3
5
7
9
12
14
16
18
1A1
1A2
1A3
1A4
1Y1
2A1
2A2
2A3
2A4
2Y1
1Y2
1Y3
1Y4
2Y2
2Y3
2Y4
2OE
1OE
Copyright © 2016, Texas Instruments Incorporated
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HCT244
,
SN74HCT244
SCLS175E MONTH 2003REVISED AUGUST 2016
SNx4HCT244 Octal Buffers and Line Drivers With 3-State Outputs
1
1 Features
1
Operating Voltage Range of 4.5 V to 5.5 V
High-Current Outputs Drive up to 15 LSTTL Loads
Low Power Consumption: 80-µA Maximum I
CC
Typical t
pd
= 13 ns
±6-mA Output Drive at 5 V
Low Input Current of 1 µA Maximum
Inputs Are TTL-Voltage Compatible
3-State Outputs Drive Bus Lines and Buffer
Memory Address Registers
2 Applications
Servers
LED Displays
Network Switches
Telecom Infrastructure
Motor Drivers
I/O Expanders
3 Description
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers,
clockdrivers, and bus-oriented receivers and
transmitters. The SNx4HCT244 devices are
organized as two 4-bit buffers or drivers with separate
output-enable (OE) inputs. When OE is low, the
device passes noninverted data from the A inputs to
the Y outputs. When OE is high, the outputs are in
the high-impedance state.
Device Information
(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74HCT244DB SSOP (20) 7.20 mm × 5.30 mm
SN74HCT244DW SOIC (20) 12.80 mm × 7.50 mm
SN74HCT244N PDIP (20) 24.33 mm × 6.35 mm
SN74HCT244NS SO (20) 12.60 mm × 5.30 mm
SN74HCT244PW TSSOP (20) 6.50 mm × 4.40 mm
SN54HCT244
CDIP (20) 24.20 mm × 6.92 mm
LCCC (20) 8.89 mm × 8.89 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)

Summary of content (30 pages)