Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Master rest Non-inverting SOIC 20

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  

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SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Operating Voltage Range of 4.5 V to 5.5 V

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 80-µA Max I

D Typical t

= 12 ns

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

D Inputs Are TTL-Voltage Compatible

D Contain Eight D-Type Flip-Flops

D Direct Clear Input

D Applications Include:

− Buffer/Storage Registers

− Shift Registers

− Pattern Generators

CLR

GND

CLK

SN54HCT273 ...J OR W PACKAGE

SN74HCT273 . . . DB, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

CLR

GND

CLK

SN54HCT273 . . . FK PACKAGE

(TOP VIEW)

description/ordering information

These devices are positive-edge-triggered D-type flip-flops with a common enable input. The ’HCT273 devices

are similar to the ’HCT377 devices, but feature a common clear enable (CLR

) input instead of a latched clock.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the

positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not

directly related to the positive-going pulse. When CLK is at either the high or low level, the D input has no effect

at the output. The circuits are designed to prevent false clocking by transitions at CLR

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 20 SN74HCT273N SN74HCT273N

SOIC − DW

Tube of 25 SN74HCT273DW

HCT273

SOIC − DW

Reel of 2000 SN74HCT273DWR

HCT273

−40°C to 85°C

SOP − NS Reel of 2000 SN74HCT273NSR HCT273

−40°C to 85°C

SSOP − DB Reel of 2000 SN74HCT273DBR HT273

Tube of 70 SN74HCT273PW

TSSOP − PW

Reel of 2000 SN74HCT273PWR

HT273

TSSOP − PW

Reel of 250 SN74HCT273PWT

HT273

CDIP − J Tube of 20 SNJ54HCT273J SNJ54HCT273J

−55°C to 125°C

CFP − W Tube of 85 SNJ54HCT273W SNJ54HCT273W

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54HCT273FK SNJ54HCT273FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (17 pages)

PAGE 1
SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003 Operating Voltage Range of 4.5 V to 5.5 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 12 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 SN54HCT273 . . .
PAGE 2
SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003 FUNCTION TABLE (each flip-flop) INPUTS CLR CLK D OUTPUT Q L X X L H ↑ H H H ↑ L L H L X Q0 logic diagram (positive logic) 1D CLK 2D 3 11 3D 4 1D 1D C1 5D 8 1D C1 R CLR 4D 7 1D C1 R 6D 13 1D C1 R 7D 14 1D C1 R 8D 17 1D C1 R 18 1D C1 R C1 R R 1 2 1Q 5 6 2Q 3Q 9 12 4Q 15 5Q 6Q 16 7Q 19 8Q logic diagram, each flip-flop (positive logic) D
PAGE 3
SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) fclock Clock frequency CLK high or low tw Pulse duration CLR low Data tsu Setup time before CLK↑ CLR inactive th Hold time data after CLK↑ TA = 25°C MIN MAX SN54HCT273 VCC 4.5 V 25 16 20 5.5 V 28 19 23 MIN SN74HCT273 MAX MIN 4.5 V 20 30 25 5.5 V 18 25 22 4.5 V 16 24 20 5.
PAGE 5
SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load TYP 30 UNIT pF PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point 3V High-Level Pulse 1.3 V 0V CL = 50 pF (see Note A) tw 1.3 V 1.3 V 0V 3V 1.3 V 3V Low-Level Pulse LOAD CIRCUIT Input 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS 1.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HCT273DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74HCT273DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74HCT273NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HCT273DBR SN74HCT273DWR SSOP DB 20 2000 367.0 367.0 38.0 SOIC DW 20 2000 367.0 367.0 45.0 SN74HCT273NSR SO NS 20 2000 367.0 367.0 45.0 SN74HCT273PWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74HCT273PWT TSSOP PW 20 250 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 17
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.