Datasheet

SN54HCT373, SN74HCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS009D – MARCH 1984 – REVISED AUGUST 2003
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Operating Voltage Range of 4.5 V to 5.5 V
High-Current 3-State True Outputs Can
Drive Up To 15 LSTTL Loads
Low Power Consumption, 80-µA Max I
CC
Typical t
pd
= 21 ns
±6-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Inputs Are TTL-Voltage Compatible
Eight High-Current Latches in a Single
Package
Full Parallel Access for Loading
description/ordering information
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches of the ’HCT373 devices are
transparent D-type latches. While the
latch-enable (LE) input is high, the Q outputs
follow the data (D) inputs. When LE is taken low,
the Q outputs are latched at the levels that were
set up at the D inputs.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–40 C to 85 C
PDIP – N Tube of 20 SN74HCT373N SN74HCT373N
–40 C to 85 C
SOIC – DW
Tube of 25 SN74HCT373DW
HCT373
–40 C to 85 C
SOIC – DW
Reel of 2000 SN74HCT373DWR
HCT373
–40
°
C to 85
°
C
SOP – NS Reel of 2000 SN74HCT373NSR HCT373
–40°C to 85°C
SSOP – DB Reel of 2000 SN74HCT373DBR HT373
TSSOP – PW
Tube of 70 SN74HCT373PW
HT373
TSSOP – PW
Reel of 2000 SN74HCT373PWR
HT373
Reel of 250 SN74HCT373PWT
–55 C to 125 C
CDIP – J Tube of 20 SNJ54HCT373J SNJ54HCT373J
–55
°
C to 125
°
C
CFP – W Tube of 85 SNJ54HCT373W SNJ54HCT373W
LCCC – FK Tube of 55 SNJ54HCT373FK SNJ54HCT373FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
3212019
910111213
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
1D
1Q
OE
5Q
5D
V
8Q
4Q
GND
LE
SN54HCT373 . . .FK PACKAGE
(TOP VIEW)
CC
SN54HCT373 . . .J OR W PACKAGE
SN74HCT373 . . .DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

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