Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Preset/reset Differential SOIC 14

 

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   

SCLS169E − DECEMBER 1982 − REVISED APRIL 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Operating Voltage Range of 4.5 V to 5.5 V

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 40-µA Max I

D Typical t

= 17 ns

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

D Inputs Are TTL-Voltage Compatible

description/ordering information

The ’HCT74 devices contain two independent

D-type positive-edge-triggered flip-flops. A low

level at the preset (PRE

) or clear (CLR) inputs sets

or resets the outputs, regardless of the levels of

the other inputs. When PRE

and CLR are inactive

(high), data at the data (D) input meeting the setup

time requirements are transferred to the outputs

on the positive-going edge of the clock (CLK)

pulse. Clock triggering occurs at a voltage level

and is not directly related to the rise time of CLK.

Following the hold-time interval, data at the

D input may be changed without affecting the

levels at the outputs.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 25 SN74HCT74N SN74HCT74N

Tube of 50 SN74HCT74D

SOIC − D

Reel of 2500 SN74HCT74DR

HCT74

SOIC − D

Reel of 250 SN74HCT74DT

HCT74

−40°C to 85°C

SOP − NS Reel of 2000 SN74HCT74NSR HCT74

−40 C to 85 C

SSOP − DB Reel of 2000 SN74HCT74DBR HT74

Tube of 90 SN74HCT74PW

TSSOP − PW

Reel of 2000 SN74HCT74PWR

HT74

TSSOP − PW

Reel of 250 SN74HCT74PWT

HT74

CDIP − J Tube of 25 SNJ54HCT74J SNJ54HCT74J

−55°C to 125°C

CFP − W Tube of 150 SNJ54HCT74W SNJ54HCT74W

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54HCT74FK SNJ54HCT74FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1CLR

1CLK

1PRE

GND

2CLR

2CLK

2PRE

SN54HCT74 ...J OR W PACKAGE

SN74HCT74 . . . D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

2CLK

2PRE

1CLK

1PRE

1CLR

2CLR

GND

SN54HCT74 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

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Summary of content (20 pages)

PAGE 1
SCLS169E − DECEMBER 1982 − REVISED APRIL 2004 Operating Voltage Range of 4.5 V to 5.5 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 40-µA Max ICC Typical tpd = 17 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible SN54HCT74 . . . J OR W PACKAGE SN74HCT74 . . .
PAGE 2
SCLS169E − DECEMBER 1982 − REVISED APRIL 2004 FUNCTION TABLE OUTPUT INPUTS PRE CLR CLK D Q Q L H X X H L H L X X H H† L L X X L H† H H ° H H L H H ° L L H H H L X Q0 Q0 † This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.
PAGE 3
SCLS169E − DECEMBER 1982 − REVISED APRIL 2004 recommended operating conditions (see Note 3) SN54HCT74 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO ∆t/∆v Output voltage 0 High-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V SN74HCT74 2 2 Input transition rise/fall time V V 0.8 VCC VCC UNIT 0 0 500 0.
PAGE 4
SCLS169E − DECEMBER 1982 − REVISED APRIL 2004 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax PRE or CLR Q or Q tpd CLK Q or Q tt Q or Q VCC MIN TA = 25°C TYP MAX SN54HCT74 MIN MAX SN74HCT74 MIN 4.5 V 27 40 18 22 5.5 V 30 46 20 24 MAX UNIT MHz 4.5 V 21 35 53 44 5.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 25-Jan-2012 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HCT74DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74HCT74DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HCT74DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HCT74DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74HCT74DR SOIC D 14 2500 367.0 367.0 38.0 SN74HCT74DT SOIC D 14 250 367.0 367.0 38.0 SN74HCT74NSR SO NS 14 2000 367.0 367.0 38.0 SN74HCT74PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74HCT74PWT TSSOP PW 14 250 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 20
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.