Datasheet

5-1
FAST AND LS TTL DATA
QUAD D FLIP-FLOP
The LSTTL/MSI SN54/74LS175 is a high speed Quad D Flip-Flop. The
device is useful for general flip-flop requirements where clock and clear inputs
are common. The information on the D inputs is stored during the LOW to
HIGH clock transition. Both true and complemented outputs of each flip-flop
are provided. A Master Reset input resets all flip-flops, independent of the
Clock or D inputs, when LOW.
The LS175 is fabricated with the Schottky barrier diode process for high
speed and is completely compatible with all Motorola TTL families.
• Edge-Triggered D-Type Inputs
• Buffered-Positive Edge-Triggered Clock
• Clock to Output Delays of 30 ns
• Asynchronous Common Reset
• True and Complement Output
• Input Clamp Diodes Limit High Speed Termination Effects
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
CONNECTION DIAGRAM DIP (TOP VIEW)
14 13 12 11 10 9
123456
7
16 15
8
V
CC
MR
Q
3
Q
3
D
3
D
2
Q
2
Q
2
CP
Q
0
Q
0
D
0
D
1
Q
1
Q
1
GND
PIN NAMES LOADING (Note a)
HIGH
LOW
D
0
–D
3
CP
MR
Q
0
–Q
3
Q
0
–Q
3
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
True Outputs (Note b)
Complemented Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
LOGIC DIAGRAM
DQ
CP
C
D
Q
CP D
3
D
2
D
1
D
0
Q
3
Q
3
Q
2
Q
2
Q
1
Q
1
Q
0
Q
0
DQ
CP
C
D
Q
MR
14
1
267
3
459
11
12
10
13
15
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
DQ
CP
C
D
Q
DQ
CP
C
D
Q
SN54/74LS175
QUAD D FLIP-FLOP
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
V
CC
= PIN 16
GND = PIN 8
12
1
236711141510
45 13
9CP
D
0
D
1
D
2
D
3
MR
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3