Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Master rest Non-inverting SOIC 20

CLK

CLR

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std.

91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DW, J, N, and W packages.

SN54273, SN54LS273, SN74273, SN74LS273

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

SDLS090 – OCTOBER 1976 – REVISED MARCH 1988

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• Contains Eight Flip-Flops With Single-Rail

Outputs

• Buffered Clock and Direct Clear Inputs

• Individual Data Input to Each Flip-Flop

• Applications Include:

Buffer/Storage Registers

Shift Registers

Pattern Generators

description

These monolithic, positive-edge-triggered flip-

flops utilize TTL circuitry to implement D-type

flip-flop logic with a direct clear input.

Information at the D inputs meeting the setup time

requirements is transferred to the Q outputs on the

positive-going edge of the clock pulse. Clock

triggering occurs at a particular voltage level and

is not directly related to the transition time of the

positive-going pulse. When the clock input is at

either the high or low level, the D input signal has

no effect ar the output.

These flip-flops are guaranteed to respond to

clock frequencies ranging form 0 to 30 megahertz

while maximum clock frequency is typically 40

megahertz. Typical power dissipation is 39

milliwatts per flip-flop for the ′273 and 10 milliwatts

for the ′LS273.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

CLEAR CLOCK D

L X X L

H ↑ HH

H ↑LL

HLXQ

SN54LS273 . . . FK PACKAGE

(TOP VIEW)

SN54273, SN74LS273 ...J OR W PACKAGE

SN74273 ...N PACKAGE

SN74LS273 . . . DW OR N PACKAGE

(TOP VIEW)

CLR

GND

CLK

3212019

910111213

CLR

GND

CLK

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (8 pages)

PAGE 1
SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 • • • • Contains Eight Flip-Flops With Single-Rail Outputs Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators SN54273, SN74LS273 . . . J OR W PACKAGE SN74273 . . . N PACKAGE SN74LS273 . . .
PAGE 2
SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 schematics of inputs and outputs ′273 EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC VCC 100 Ω NOM Req INPUT OUTPUT Clear: Req = 3 kΩ NOM Clock: Req = 6 kΩ NOM All other inputs: Req = 8 kΩ NOM ′LS273 TYPICAL OF ALL OUTPUTS EQUIVALENT OF EACH INPUT VCC 120 Ω NOM VCC 20 kΩ NOM INPUT OUTPUT logic diagram (positive logic) CLOCK 11 1D 2D 3D 4D 3 4 7 8 1D 1D C1 R CLEAR
PAGE 3
SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 switching characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS fmax tPHL Maximum clock frequency tPLH tPHL Propagation delay time, low-to-high-level output from clock MIN TYP 30 40 CL = 15 pF, RL = 400 Ω Ω, See Note 3 Propagation delay time, high-to-low-level output from clear Propagation delay time, high-to-low-level output from clock MAX UNIT MHz 18 27 ns 17 27
PAGE 5
SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VIH VIL High-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL II IIH IIL IOS SN54LS273 TYP‡ MAX TEST CONDITIONS† PARAMETER MIN 2 SN74LS273 TYP‡ MAX MIN 2 Low-level input voltage UNIT V 0.7 0.8 V –1.5 –1.
PAGE 6
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LS273DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74LS273NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.
PAGE 7
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LS273DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LS273NSR SO NS 20 2000 367.0 367.0 45.
PAGE 8
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.