Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver SOIC 14

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SCES124L − DECEMBER 1997 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Max t

of 6 ns at 5 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2.3 V at V

= 3.3 V, T

= 25°C

D Support Mixed-Mode Voltage Operation on

All Ports

D I

off

Supports Partial-Power-Down Mode

Operation

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

1OE

2OE

GND

4OE

3OE

SN54LV125A ...J OR W PACKAGE

SN74LV125A . . . D, DB, DGV, N, NS,

OR PW PACKAGE

(TOP VIEW)

3212019

910111213

3OE

2OE

1OE

4OE

GND

SN54LV125A . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

SN74LV125A . . . RGY PACKAGE

(TOP VIEW)

114

4OE

3OE

2OE

1OE

GND

description/ordering information

The ‘LV125A quadruple bus buffer gates are designed for 2-V to 5.5-V V

operation.

These devices feature independent line drivers with 3-state outputs. Each output is disabled when the

associated output-enable (OE

) input is high.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 25 SN74LV125AN SN74LV125AN

QFN − RGY Reel of 1000 SN74LV125ARGYR LV125A

SOIC − D

Tube of 50 SN74LV125AD

LV125A

SOIC − D

Reel of 2500 SN74LV125ADR

LV125A

−40°C to 85°C

SOP − NS Reel of 2000 SN74LV125ANSR 74LV125A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74LV125ADBR LV125A

Tube of 90 SN74LV125APW

TSSOP − PW

Reel of 2000 SN74LV125APWR

LV125A

TSSOP − PW

Reel of 250 SN74LV125APWT

LV125A

TVSOP − DGV Reel of 2000 SN74LV125ADGVR LV125A

CDIP − J Tube of 25 SNJ54LV125AJ SNJ54LV125AJ

−55°C to 125°C

CFP − W Tube of 150 SNJ54LV125AW SNJ54LV125AW

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54LV125AFK SNJ54LV125AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (24 pages)

PAGE 1
SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP (Output Ground Bounce) 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y 1A 1Y 2OE 2A 2Y 14 1A 1OE NC VCC 4OE 1 2 13 4OE 3 12 4A 4 11 4Y 5 10 3OE 9 3A 6 7 8 SN54LV125A . . .
PAGE 2
SCES124L − DECEMBER 1997 − REVISED APRIL 2005 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for partial-power-down applications using Ioff.
PAGE 3
SCES124L − DECEMBER 1997 − REVISED APRIL 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 4
SCES124L − DECEMBER 1997 − REVISED APRIL 2005 recommended operating conditions (see Note 5) SN54LV125A VCC VIH Supply voltage High-level input voltage VIL Low-level input voltage VI Input voltage VO Output voltage IOH IOL ∆t/∆v High-level output current Low-level output current Input transition rise or fall rate VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V SN74LV125A MIN MAX 2 5.5 1.
PAGE 5
SCES124L − DECEMBER 1997 − REVISED APRIL 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV125A PARAMETER VOH VOL TEST CONDITIONS IOH = −50 µA IOH = −2 mA MIN 2 V to 5.5 V IOH = −8 mA IOH = −16 mA IOL = 50 µA IOL = 2 mA IOL = 8 mA IOL = 16 mA VI = 5.5 V or GND VO = VCC or GND ICC Ioff VI = VCC or GND, IO = 0 VI or VO = 0 to 5.
PAGE 6
SCES124L − DECEMBER 1997 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A Y ten tdis OE Y OE tpd A ten tdis OE Y OE Y PARAMETER LOAD CAPACITANCE MIN free-air TA = 25°C TYP MAX temperature SN54LV125A range, SN74LV125A MIN MAX MIN MAX 3.4* 5.5* 1* 6.5* 1 6.5 3.4* 5.1* 1* 6* 1 6 Y 3.2* 6.
PAGE 7
SCES124L − DECEMBER 1997 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain CL (see Note A) CL (see Note A) Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com (3) 4-Oct-2010 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LV125ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74LV125ADGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV125ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV125ADBR SSOP DB 14 2000 367.0 367.0 38.0 SN74LV125ADGVR TVSOP DGV 14 2000 367.0 367.0 35.0 SN74LV125ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LV125ANSR SO NS 14 2000 367.0 367.0 38.0 SN74LV125APWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74LV125APWT TSSOP PW 14 250 367.0 367.0 35.
PAGE 13
PAGE 14
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 24
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.