Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver SOIC 14

 

   

  

SCES131H − MARCH 1998 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Max t

of 6.5 ns at 5 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2.3 V at V

= 3.3 V, T

= 25°C

D Support Mixed-Mode Voltage Operation on

All Ports

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

These quadruple bus buffer gates are designed

for 2-V to 5.5-V V

operation.

The ’LV126A devices feature independent line

drivers with 3-state outputs. Each output is

disabled when the associated output-enable (OE)

input is low.

To ensure the high-impedance state during power

up or power down, OE should be tied to GND

through a pulldown resistor; the minimum value of

the resistor is determined by the current-sourcing

capability of the driver.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC − D

Tube of 50 SN74LV126AD

LV126A

SOIC − D

Reel of 2500 SN74LV126ADR

LV126A

SOP − NS Reel of 2000 SN74LV126ANSR 74LV126A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74LV126ADBR LV126A

−40°C to 85°C

Tube of 90 SN74LV126APW

TSSOP − PW

Reel of 2000 SN74LV126APWR

LV126A

TSSOP − PW

Reel of 250 SN74LV126APWT

LV126A

TVSOP − DGV Reel of 2000 SN74LV126ADGVR LV126A

CDIP − J Tube of 25 SNJ54LV126AJ SNJ54LV126AJ

−55°C to 125°C

CFP − W Tube of 150 SNJ54LV126AW SNJ54LV126AW

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54LV126AFK SNJ54LV126AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

   ! "#$%&'( $#()(! *

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,#"%$#( -,#$'!!(4 "#'! (# ('$'!!),/3 ($/%"' '!(4 #+ )//

-),)&'',!0

1OE

2OE

GND

4OE

3OE

SN54LV126A ...J OR W PACKAGE

SN74LV126A ...D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

3OE

2OE

1OE

4OE

GND

SN54LV126A . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (18 pages)

PAGE 1
SCES131H − MARCH 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP (Output Ground Bounce) D D D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.
PAGE 2
SCES131H − MARCH 1998 − REVISED APRIL 2005 FUNCTION TABLE (each buffer) INPUTS OE A OUTPUT Y H H H H L L L X Z logic diagram (positive logic) 1OE 1A 2OE 2A 1 2 3OE 3 1Y 3A 4 5 4OE 6 2Y 4A 10 9 8 3Y 13 12 11 4Y Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . .
PAGE 3
SCES131H − MARCH 1998 − REVISED APRIL 2005 recommended operating conditions (see Note 4) SN54LV126A VCC VIH High-level input voltage VIL Low-level input voltage VI Input voltage VO Output voltage IOH IOL ∆t/∆v MIN MAX 2 5.5 Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 1.5 Low-level output current Input transition rise or fall rate MIN MAX 2 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.
PAGE 4
SCES131H − MARCH 1998 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A Y ten tdis OE Y OE tpd A ten tdis OE Y OE Y PARAMETER LOAD CAPACITANCE MIN TA = 25°C TYP MAX SN74LV126A MIN MAX MIN MAX 13* 1* 15.5* 1 15.5 13* 1* 15.5* 1 15.5 Y 5.7* 14.7* 1* 17* 1 17 Y 9.2 16.5 1 18.5 1 18.
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SCES131H − MARCH 1998 − REVISED APRIL 2005 noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) SN74LV126A PARAMETER MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.3 0.8 V VOL(V) Quiet output, minimum dynamic VOL −0.2 −0.8 V VOH(V) Quiet output, minimum dynamic VOH 3.1 VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage V 2.31 V 0.97 V VCC 3.
PAGE 6
SCES131H − MARCH 1998 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain CL (see Note A) CL (see Note A) Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Dat
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LV126ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74LV126ADGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV126ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV126ADBR SSOP DB 14 2000 367.0 367.0 38.0 SN74LV126ADGVR TVSOP DGV 14 2000 367.0 367.0 35.0 SN74LV126ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LV126ANSR SO NS 14 2000 367.0 367.0 38.0 SN74LV126APWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74LV126APWT TSSOP PW 14 250 367.0 367.0 35.
PAGE 11
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 18
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.