Datasheet

9
4
5
6
7
8
18
17
16
15
14
1B
1A
NC
3Y
3A
V
4B
2Y
GND
NC
SN54LV132A...FK PACKAGE
(TOP VIEW)
CC
NC – No internal connection
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
4A
NC
4Y
NC
3B
1Y
NC
2A
NC
2B
SN54LV132A...JO OR W PACKAGE
(TOP VIEW)
SN74LV132A...D, DB, DGV, NS, OR PW PACKAGE
10 11 12 13
3 2 1 20 19
SN54LV132A, SN74LV132A
www.ti.com SCLS394I –APRIL 1999–REVISED JUNE 2010
QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
Check for Samples: SN54LV132A, SN74LV132A
1
FEATURES
• 2-V to 5.5-V V
CC
Operation
• Max t
pd
of 9 ns at 5 V
• Typical V
OLP
(Output Ground Bounce) < 0.8 V
at V
CC
= 3.3 V, T
A
= 25°C
• Typical V
OHV
(Output V
OH
Undershoot) > 2.3 V
at V
CC
= 3.3 V, T
A
= 25°C
• Support Mixed-Mode Voltage Operation on All
Ports
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION
The 'LV132A devices are quadruple positive-NAND gates designed for 2-V to 5.5-V V
CC
operation.
The 'LV132A devices perform the Boolean function Y = A • B or Y = A + B in positive logic.
Each circuit functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels
for positive- and negative-going signals.
These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give
clean jitter-free output signals.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.