Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Counter Binary counter 74LV-A Positive slope 95 MHz TSSOP 16

 

   

SCLS404F − APRIL 1998 − REVISED DECEMBER 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Max t

of 9.5 ns at 5 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2.3 V at V

= 3.3 V, T

= 25°C

D Support Mixed-Mode Voltage Operation on

All Ports

D Internal Look-Ahead for Fast Counting

D Carry Output for n-Bit Cascading

D Synchronous Counting

D Synchronously Programmable

D I

off

Supports Partial-Power-Down Mode

Operation

D Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

The ’LV161A devices are 4-bit synchronous

binary counters designed for 2-V to 5.5-V V

operation.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC − D

Tube of 40 SN74LV161AD

LV161A

SOIC − D

Reel of 2500 SN74LV161ADR

LV161A

SOP − NS Reel of 2000 SN74LV161ANSR 74LV161A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74LV161ADBR LV161A

−40°C to 85°C

Tube of 90 SN74LV161APW

TSSOP − PW

Reel of 2000 SN74LV161APWR

LV161A

TSSOP − PW

Reel of 250 SN74LV161APWT

LV161A

TVSOP − DGV Reel of 2000 SN74LV161ADGVR LV161A

CDIP − J Tube of 25 SNJ54LV161AJ SNJ54LV161AJ

−55°C to 125°C

CFP − W Tube of 150 SNJ54LV161AW SNJ54LV161AW

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54LV161AFK SNJ54LV161AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

    !"#$ $%$ &

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)#'%$ )#( # #(" ' #-% $(!"#$ %$%( .%((%$/,

&(!$ )(#$0 # $ $##%(+/ $+!# #$0 ' %++

)%(%"##(,

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54LV161A ...J OR W PACKAGE

SN74LV161A . . . D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

SN54LV161A . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

CLR

CLK

ENP

GND

RCO

ENT

LOAD

3 2 1 20 19

910111213

CLK

CLR

LOAD

ENT

RCO

ENP

GND

Summary of content (23 pages)

PAGE 1
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP (Output Ground Bounce) D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC RCO QA QB QC QD ENT LOAD SN54LV161A . . .
PAGE 2
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 description/ordering information (continued) These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating.
PAGE 3
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 logic diagram (positive logic) LOAD ENT ENP 9 10 15 LD† 7 RCO CK† CLK CLR A B C D 2 1 CK LD R M1 G2 1, 2T/1C3 G4 3D 4R 3 M1 G2 1, 2T/1C3 G4 3D 4R 4 M1 G2 1, 2T/1C3 G4 3D 4R 5 M1 G2 1, 2T/1C3 G4 3D 4R 6 14 13 12 11 QA QB QC QD † For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram.
PAGE 4
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 logic symbol, each D/T flip-flop LD (Load) M1 TE (Toggle Enable) G2 CK (Clock) 1, 2T/1C3 G4 D (Inverted Data) 3D R (Inverted Reset) 4R Q (Output) logic diagram, each D/T flip-flop (positive logic) CK LD TE LD† TG TG LD† Q TG TG CK† D TG CK† R † The origins of LD and CK are shown in the overall logic diagram of the device.
PAGE 5
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 typical clear, preset, count, and inhibit sequence The following sequence is illustrated below: 1. Clear outputs to zero (asynchronous) 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4.
PAGE 6
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 7
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 recommended operating conditions (see Note 4) SN54LV161A VCC VIH High-level input voltage VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 2 5.5 Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 2 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 0.5 Output voltage 0 0 VCC −50 V VCC × 0.3 5.
PAGE 8
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw tsu th Pulse duration Setup time before CLK↑ SN54LV161A MIN MAX SN74LV161A MIN CLK high or low 7 7 7 CLR low 7 7 7 CLR 4.5 4.5 4.5 Data (A, B, C, and D) 7.5 8.5 8.5 ENP, ENT 9.5 11 11 LOAD low 10 11.5 11.5 1.5 1.5 1.
PAGE 9
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax CLK tpd tPHL CLR CLK tpd tPHL SN74LV161A CL = 15 pF 50* 125* 40* 40 CL = 50 pF 30 95 25 25 MIN MAX MIN MAX 16.2* 1* 19.5* 1 19.5 RCO (count mode) 8.9* 17* 1* 20.5* 1 20.5 11.9* 20.6* 1* 24.
PAGE 10
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax TA = 25°C TYP MAX tpd* CL = 15 pF* 80* 165* 70* 70 CL = 50 pF 55 125 50 50 tPHL* CLR CLK tpd tPHL MIN MAX 15* 1 15 6.7 13.6 1* 16* 1 16 8.6 17.2 1* 20* 1 20 RCO 6.2 12.3 1* 14.5* 1 14.
PAGE 11
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax CLK tpd 220 115* 115 95 165 85 85 MIN MAX 9.5* 1 9.5 RCO (count mode) 5.1* 8.1* 1* 9.5* 1 9.5 6.3* 10.3* 1* 12* 1 12 RCO 4.8* 8.1* 1* 9.5* 1 9.5 Q 4.9* 9* 1* 10.5* 1 10.5 RCO 5.5* 8.
PAGE 12
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input 50% VCC th VCC 50% VCC Data Input 50
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.
PAGE 14
PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.6 2.5 12.0 16.0 Q1 SN74LV161ADBR SSOP DB 16 2000 330.0 16.4 8.2 SN74LV161ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV161ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV161ADBR SSOP DB 16 2000 367.0 367.0 38.0 SN74LV161ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0 SN74LV161ADR SOIC D 16 2500 333.2 345.9 28.6 SN74LV161ANSR SO NS 16 2000 367.0 367.0 38.0 SN74LV161APWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74LV161APWT TSSOP PW 16 250 367.0 367.0 35.
PAGE 17
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 18
PAGE 19
PAGE 20
PAGE 21
PAGE 22
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 23
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.