Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Counter Binary counter 74LV Positive slope 90 MHz SOIC 16 N

SN54LV163A, SN74LV163A

4-BIT SYNCHRONOUS BINARY COUNTERS

SCLS405F − APRIL 1998 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Max t

of 9.5 ns at 5 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2.3 V at V

= 3.3 V, T

= 25°C

D Support Mixed-Mode Voltage Operation on

All Ports

D Internal Look Ahead for Fast Counting

D Carry Output for n-Bit Cascading

D Synchronous Counting

D Synchronously Programmable

D I

off

Supports Partial-Power-Down Mode

Operation

D Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

SN54LV163A ...J OR W PACKAGE

SN74LV163A ...D, DB, DGV, NS,

OR PW PACKAGE

(TOP VIEW)

SN54LV163A . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

CLR

CLK

ENP

GND

RCO

ENT

LOAD

3 2 1 20 19

910111213

CLK

CLR

LOAD

ENT

RCO

ENP

GND

SN74LV163A . . . RGY PACKAGE

(TOP VIEW)

116

RCO

ENT

CLK

ENP

GND

CLR

LOAD

description/ordering information

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN − RGY Reel of 1000 SN74LV163ARGYR LV163A

SOIC D

Tube of 40 SN74LV163AD

LV163A

SOIC − D

Reel of 2500 SN74LV163ADR

LV163A

SOP − NS Reel of 2000 SN74LV163ANSR 74LV163A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74LV163ADBR LV163A

40 C

85 C

Tube of 90 SN74LV163APW

TSSOP − PW

Reel of 2000 SN74LV163APWR

LV163A

TSSOP

Reel of 250 SN74LV163APWT

LV163A

TVSOP − DGV Reel of 2000 SN74LV163ADGVR LV163A

CDIP − J Tube of 25 SNJ54LV163AJ SNJ54LV163AJ

−55°C to 125°C

CFP − W Tube of 150 SNJ54LV163AW SNJ54LV163AW

LCCC − FK Tube of 55 SNJ54LV163AFK SNJ54LV163AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Summary of content (25 pages)

PAGE 1
SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 2 15 3 14 4 13 12 5 6 11 7 10 8 9 VCC RCO QA QB QC QD ENT LOAD CLK A B C D ENP 16 CLK CLR NC VCC RCO 1 SN54LV163A . . .
PAGE 2
SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 description/ordering information (continued) The ’LV163A devices are 4-bit synchronous binary counters designed for 2-V to 5.5-V VCC operation. These synchronous, presettable counters feature an internal carry look ahead for application in high-speed counting designs. The ’LV163A devices are 4-bit binary counters.
PAGE 3
SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 logic diagram (positive logic) LOAD ENT ENP 9 10 15 LD† 7 RCO CK† CLK CLR 2 1 CK LD R A B C D M1 G2 1, 2T/1C3 G4 3D 4R 3 M1 G2 1, 2T/1C3 G4 3D 4R 4 M1 G2 1, 2T/1C3 G4 3D 4R 5 M1 G2 1, 2T/1C3 G4 3D 4R 6 14 13 12 11 QA QB QC QD † For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram.
PAGE 4
SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 logic diagram, each D/T flip-flop (positive logic) CK LD TE LD† TG TG Q TG LD† TG CK† D TG CK† R † 4 The origins of LD and CK are shown in the overall logic diagram of the device.
PAGE 5
SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 typical clear, preset, count, and inhibit sequence The following sequence is illustrated below: 1. Clear outputs to zero (synchronous) 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4.
PAGE 6
SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 7
SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 recommended operating conditions (see Note 5) SN54LV163A VCC MIN MAX 2 5.5 Supply voltage VCC = 2 V VIH High level input voltage High-level 1.5 Low level input voltage Low-level VI Input voltage VO Output voltage VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7 Input transition rise or fall rate TA Operating free-air temperature V V 0.5 0.5 VCC × 0.3 VCC × 0.
PAGE 8
SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 timing requirements over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) free-air TA = 25°C MIN tw Pulse duration, CLK high or low Set p time before CLK↑ Setup th Hold time, all synchronous inputs after CLK↑ SN54LV163A MAX 7 6 Data (A, B, C, and D) 7.5 8.5 8.5 ENP, ENT 9.5 11 11 10 11.5 11.5 1.5 1.5 1.
PAGE 9
SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax TA = 25°C C CLK ENT CL = 15 pF 50* 115* 40* 40 CL = 50 pF 30 90 25 25 tpd RCO (preset mode) ENT MIN MAX MIN MAX UNIT MHz 8.5* 16.2* 1* 19.5* 1 19.5 9.1* 17* 1* 20.5* 1 20.5 12.1* 20.6* 1* 24.5* 1 24.5 8.7* 15.
PAGE 10
SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax TA = 25°C C CLK CL = 15 pF 135* 210* 115* 115 CL = 50 pF 95 160 85 85 tpd MIN MAX MIN MAX 1* 9.5* 1 9.5 5.2* 8.1* 1* 9.5* 1 9.5 6.4* 10.3* 1* 12* 1 12 RCO 4.9* 8.1* 1* 9.5* 1 9.5 Q 6.1 10.1 1 11.5 1 11.5 6.
PAGE 11
SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VCC Test Point From Output Under Test From Output Under Test RL = 1 kΩ S1 Open TEST GND LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain CL (see Note A) CL (see Note A) Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50
PAGE 12
PACKAGE OPTION ADDENDUM www.ti.
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2009 Orderable Device Status (1) Package Type Package Drawing SN74LV163ARGYRG4 ACTIVE VQFN RGY Pins Package Eco Plan (2) Qty 16 3000 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.6 2.5 12.0 16.0 Q1 SN74LV163ADBR SSOP DB 16 2000 330.0 16.4 8.2 SN74LV163ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV163ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV163ADBR SSOP DB 16 2000 367.0 367.0 38.0 SN74LV163ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0 SN74LV163ADR SOIC D 16 2500 333.2 345.9 28.6 SN74LV163ANSR SO NS 16 2000 367.0 367.0 38.0 SN74LV163APWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74LV163APWT TSSOP PW 16 250 367.0 367.0 35.
PAGE 16
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 17
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 25
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.