Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Shift register Shift register Push pull SOIC 16 N

 

   

SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Max t

of 10.5 ns at 5 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2.3 V at V

= 3.3 V, T

= 25°C

D I

off

Supports Partial-Power-Down-Mode

Operation

D Synchronous Load

D Direct Overriding Clear

D Parallel-to-Serial Conversion

D Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

SN54LV166A ...J OR W PACKAGE

SN74LV166A . . . D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

SN54LV166A . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

SER

CLK INH

CLK

GND

SH/LD

CLR

3212019

910111213

CLK INH

SER

CLR

SH/LD

CLK

GND

description/ordering information

The ’LV166A devices are 8-bit parallel-load shift registers, designed for 2-V to 5.5-V V

operation.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC − D

Tube of 40 SN74LV166AD

LV166A

SOIC − D

Reel of 2500 SN74LV166ADR

LV166A

SOP − NS Reel of 2000 SN74LV166ANSR 74LV166A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74LV166ADBR LV166A

−40°C to 85°C

Tube of 90 SN74LV166APW

TSSOP − PW

Reel of 2000 SN74LV166APWR

LV166A

TSSOP − PW

Reel of 250 SN74LV166APWT

LV166A

TVSOP − DGV Reel of 2000 SN74LV166ADGVR LV166A

CDIP − J Tube of 25 SNJ54LV166AJ SNJ54LV166AJ

−55°C to 125°C

CFP − W Tube of 150 SNJ54LV166AW SNJ54LV166AW

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54LV166AFK SNJ54LV166AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (19 pages)

PAGE 1
SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP (Output Ground Bounce) D D D D Direct Overriding Clear D Parallel-to-Serial Conversion D Latch-Up Performance Exceeds 100 mA Per <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.
PAGE 2
SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005 description/ordering information (continued) The ’LV166A parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/ load (SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse.
PAGE 3
SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005 logic diagram (positive logic) A SH/LD SER B 2 15 C D 3 4 1D C1 R 1D C1 R E F G H 5 10 11 12 14 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1 CLK INH CLK CLR 1D C1 R 6 7 9 13 QH Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
PAGE 4
SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 5
SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005 recommended operating conditions (see Note 4) SN54LV166A VCC VIH High-level input voltage VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 2 5.5 Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 2 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 Output voltage UNIT V V 0.5 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.
PAGE 6
SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX CLR low tw Pulse duration CLK high or low CLK INH before CLK↑ Data before CLK↑ tsu Setup time SH/LD before CLK↑ SER before CLK↑ CLR↑ inactive before CLK↑ th Hold time Data after CLK↑ SN54LV166A MIN MAX SN74LV166A MIN 8 9 9 8.
PAGE 7
SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 2.5 V ± 0.
PAGE 8
SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input 50% VCC th VCC 50% VCC Data Input
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.6 2.5 12.0 16.0 Q1 SN74LV166ADBR SSOP DB 16 2000 330.0 16.4 8.2 SN74LV166ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV166ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV166ADBR SSOP DB 16 2000 367.0 367.0 38.0 SN74LV166ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0 SN74LV166ADR SOIC D 16 2500 333.2 345.9 28.6 SN74LV166ANSR SO NS 16 2000 367.0 367.0 38.0 SN74LV166APWR TSSOP PW 16 2000 367.0 367.0 35.
PAGE 13
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 14
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PAGE 18
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 19
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.