Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Master rest Non-inverting SOIC 16

 

  

 

SCLS401G − APRIL 1998 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Max t

of 8.5 ns at 5 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2.3 V at V

= 3.3 V, T

= 25°C

D Support Mixed-Mode Voltage Operation on

All Ports

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

The ’LV174A devices are hex D-type flip-flops

designed for 2-V to 5.5-V V

operation.

These devices are positive-edge-triggered

flip-flops with a direct clear (CLR

) input.

Information at the data (D) inputs meeting the

setup time requirements is transferred to the

outputs on the positive-going edge of the clock

pulse. Clock triggering occurs at a particular

voltage level and is not directly related to the

transition time of the positive-going edge of the

clock pulse. When the clock (CLK) input is at

either the high or low level, the D-input signal has

no effect at the output.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC − D

Tube of 40 SN74LV174AD

LV174A

SOIC − D

Reel of 2500 SN74LV174ADR

LV174A

SOP − NS Reel of 2000 SN74LV174ANSR 74LV174A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74LV174ADBR LV174A

−40°C to 85°C

Tube of 90 SN74LV174APW

TSSOP − PW

Reel of 2000 SN74LV174APWR

LV174A

TSSOP − PW

Reel of 250 SN74LV174APWT

LV174A

TVSOP − DGV Reel of 2000 SN74LV174ADGVR LV174A

CDIP − J Tube of 25 SNJ54LV174AJ SNJ54LV174AJ

−55°C to 125°C

CFP − W Tube of 150 SNJ54LV174AW SNJ54LV174AW

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54LV174AFK SNJ54LV174AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

    !"#$% !%&% 

 %'(#&% !"(($% & ' )"*+!&% &$, ("! !%'(# 

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("!% )(!$%0 $ % %$!$&(+/ %!+"$ $%0 ' &++

)&(&#$$(,

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54LV174A ...J OR W PACKAGE

SN74LV174A . . . D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

SN54LV174A . . . FK PACKAGE

(TOP VIEW)

CLR

CLK

GND

CLR

GND

CLK

NC − No internal connection

Summary of content (16 pages)

PAGE 1
SCLS401G − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP (Output Ground Bounce) D D D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.
PAGE 2
SCLS401G − APRIL 1998 − REVISED APRIL 2005 FUNCTION TABLE INPUTS CLR CLK OUTPUT Q D L X X L H ↑ H H H ↑ L L H L X Q0 logic diagram (positive logic) 1 CLR CLK 1D 9 3 1D C1 2 1Q R To Five Other Channels Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
SCLS401G − APRIL 1998 − REVISED APRIL 2005 recommended operating conditions (see Note 4) SN54LV174A VCC VIH High-level input voltage VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 2 5.5 Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 1.5 2 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 Output voltage UNIT V V 0.5 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 5.
PAGE 4
SCLS401G − APRIL 1998 − REVISED APRIL 2005 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) MIN tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ TA = 25°C TYP MAX SN54LV174A MIN MAX SN74LV174A MIN CLR low 6 6.5 6.5 CLK high or low 7 7 7 8.5 9.5 9.5 4 4 4 −0.
PAGE 5
SCLS401G − APRIL 1998 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax TA = 25°C TYP MAX Q CLK 95* 170* 80* 80 CL = 50 pF 55 130 50 50 CL = 15 pF CL = 50 pF MIN MAX range, SN74LV174A CL = 15 pF Q CLK SN54LV174A MIN CLR tpd temperature LOAD CAPACITANCE CLR tpd free-air MIN MAX MHz 4.5* 11.4* 1* 13.
PAGE 6
SCLS401G − APRIL 1998 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input 50% VCC th VCC 50% VCC Data Input 50% VCC 0
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74LV174ADGVR TVSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) 8.0 12.0 Q1 DGV 16 2000 330.0 12.4 6.8 4.0 1.6 W Pin1 (mm) Quadrant SN74LV174ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV174ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV174ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0 SN74LV174ADR SOIC D 16 2500 333.2 345.9 28.6 SN74LV174ANSR SO NS 16 2000 367.0 367.0 38.0 SN74LV174APWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74LV174APWT TSSOP PW 16 250 367.0 367.0 35.
PAGE 11
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.