Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Multivibrator Monostable 13.2 ns TSSOP 16

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  

SCLS450G − DECEMBER 1999 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Max t

of 11 ns at 5 V

D Support Mixed-Mode Voltage Operation on

All Ports

D Schmitt-Trigger Circuitry on A, B, and CLR

Inputs for Slow Input Transition Rates

D Overriding Clear Terminates Output Pulse

D Glitch-Free Power-Up Reset on Outputs

D I

off

Supports Partial-Power-Down Mode

Operation

D Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

SN54LV221A ...J OR W PACKAGE

SN74LV221A . . . D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

SN54LV221A . . . FK PACKAGE

(TOP VIEW)

1CLR

ext

GND

ext

2CLR

3212019

910111213

ext

2CLR

1CLR

ext

GND

NC − No internal connection

ext

description/ordering information

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC − D

Tube of 40 SN74LV221AD

LV221A

SOIC − D

Reel of 2500 SN74LV221ADR

LV221A

SOP − NS Reel of 2000 SN74LV221ANSR 74LV221A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74LV221ADBR LV221A

−40°C to 85°C

Tube of 90 SN74LV221APW

TSSOP − PW

Reel of 2000 SN74LV221APWR

LV221A

TSSOP − PW

Reel of 250 SN74LV221APWT

LV221A

TVSOP − DGV Reel of 2000 SN74LV221ADGVR LV221A

CDIP − J Tube of 25 SNJ54LV221AJ SNJ54LV221AJ

−55°C to 125°C

CFP − W Tube of 150 SNJ54LV221AW SNJ54LV221AW

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54LV221AFK SNJ54LV221AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (23 pages)

PAGE 1
SCLS450G − DECEMBER 1999 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 11 ns at 5 V D Support Mixed-Mode Voltage Operation on D D D D Ioff Supports Partial-Power-Down Mode D All Ports Schmitt-Trigger Circuitry on A, B, and CLR Inputs for Slow Input Transition Rates Overriding Clear Terminates Output Pulse Glitch-Free Power-Up Reset on Outputs D SN54LV221A . . .
PAGE 2
SCLS450G − DECEMBER 1999 − REVISED APRIL 2005 description/ordering information (continued) The ’LV221A devices are dual multivibrators designed for 2-V to 5.5-V VCC operation. Each multivibrator has a negative-transition-triggered (A) input and a positive-transition-triggered (B) input, either of which can be used as an inhibit input. These edge-triggered multivibrators feature output pulse-duration control by three methods.
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SCLS450G − DECEMBER 1999 − REVISED APRIL 2005 FUNCTION TABLE (each multivibrator) INPUTS CLR OUTPUTS A B Q Q FUNCTION L X X L H Reset H H X L H Inhibit H X L L H Inhibit H L ↑ Outputs enabled H ↑† ↓ H Outputs enabled L H Outputs enabled † This condition is true only if the output of the latch formed by the NAND gate has been conditioned to the logic 1 state prior to CLR going high.
PAGE 4
SCLS450G − DECEMBER 1999 − REVISED APRIL 2005 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
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SCLS450G − DECEMBER 1999 − REVISED APRIL 2005 recommended operating conditions (see Note 4) SN54LV221A VCC VIH Supply voltage High-level input voltage VIL Low-level input voltage VI VO Input voltage IOH IOL VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.
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SCLS450G − DECEMBER 1999 − REVISED APRIL 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV221A PARAMETER IOH = −50 µA IOH = −2 mA VOH ICC MIN 2 V to 5.5 V VI = 5.5 V or GND Quiescent VI = VCC or GND, Active state (per circuit) Ioff 3V 2.48 2.48 4.5 V 3.8 TYP MAX 3.8 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V 0.55 0.55 2 V to 5.5 V ±2.5 ±2.
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SCLS450G − DECEMBER 1999 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER tpd tpd FROM (INPUT) TO (OUTPUT) A or B Q or Q CLR Q or Q CLR trigger TEST CONDITIONS MIN free-air TA = 25°C TYP MAX temperature SN54LV221A SN74LV221A MIN MAX MIN MAX 14.6* 31.4* 1* 37* 1 37 13.2* 25* 1* 29.5* 1 29.5 Q or Q 15.
PAGE 8
SCLS450G − DECEMBER 1999 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tpd tpd FROM (INPUT) TO (OUTPUT) A or B Q or Q CLR Q or Q CLR trigger TEST CONDITIONS MIN free-air TA = 25°C TYP MAX temperature SN54LV221A SN74LV221A MIN MAX MIN MAX 7.1* 12* 1* 14* 1 14 6.5* 9.4* 1* 11* 1 11 Q or Q 7.3* 12.
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SCLS450G − DECEMBER 1999 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point tw CL (see Note A) VCC Inputs or Outputs 50% VCC 50% VCC 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATION VCC Input A (see Note B) 50% VCC 0V VCC Input B (see Note B) 50% VCC 50% VCC 0V 50% VCC tPLH VOH In-Phase Output 50% VCC In-Phase Output VOL VOH VOL 50% VCC Out-of-Phase Output VOH 50% VCC VOL
PAGE 10
SCLS450G − DECEMBER 1999 − REVISED APRIL 2005 APPLICATION INFORMATION caution in use To prevent malfunctions due to noise, connect a high-frequency capacitor between VCC and GND, and keep the wiring between the external components and Cext and Rext/Cext terminals as short as possible.
PAGE 11
SCLS450G − DECEMBER 1999 − REVISED APRIL 2005 APPLICATION INFORMATION† OUTPUT PULSE DURATION vs EXTERNAL TIMING CAPACITANCE OUTPUT PULSE DURATION vs EXTERNAL TIMING CAPACITANCE 1.00E+07 1.00E+07 VCC = 4.5 V TA = 25°C 1.00E+06 t w − Output Pulse Duration − ns t w − Output Pulse Duration − ns VCC = 3 V TA = 25°C RT = 1 MΩ 1.00E+05 RT = 100 kΩ 1.00E+04 RT = 10 kΩ 1.00E+03 1.00E+06 RT = 1 MΩ 1.00E+05 RT = 100 kΩ 1.
PAGE 12
SCLS450G − DECEMBER 1999 − REVISED APRIL 2005 APPLICATION INFORMATION† OUTPUT PULSE DURATION CONSTANT vs SUPPLY VOLTAGE EXTERNAL CAPACITANCE vs MULTIPLIER FACTOR 1.20 For Capacitor Values of 0.001 µF or Greater, K = 1.0 (K is Independent of R) Output Pulse Duration Constant − K C T − External Capacitor Value − µF 0.001 0.0001 0.00001 TA = 25°C VCC = 5 V 1.00 1.50 2.00 2.50 3.00 3.50 4.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 14
PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74LV221ADGVR TVSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) 8.0 12.0 Q1 DGV 16 2000 330.0 12.4 6.8 4.0 1.6 W Pin1 (mm) Quadrant SN74LV221ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV221ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV221ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0 SN74LV221ADR SOIC D 16 2500 333.2 345.9 28.6 SN74LV221ANSR SO NS 16 2000 367.0 367.0 38.0 SN74LV221APWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74LV221APWT TSSOP PW 16 250 367.0 367.0 35.
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.