Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Master rest Non-inverting SOIC 20

 

  

 

SCLS399J − APRIL 1998 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Max t

of 10.5 ns at 5 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2.3 V at V

= 3.3 V, T

= 25°C

D I

off

Supports Partial-Power-Down Mode

Operation

D Support Mixed-Mode Voltage Operation on

All Ports

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

CLR

GND

CLK

SN54LV273A ...J OR W PACKAGE

SN74LV273A . . . DB, DGV, DW, NS,

OR PW PACKAGE

(TOP VIEW)

3212019

910111213

CLR

GND

CLK

SN54LV273A . . . FK PACKAGE

(TOP VIEW)

SN74LV273A . . . RGY PACKAGE

(TOP VIEW)

120

10 11

CLR

CLK

description/ordering information

The ’LV273A devices are octal D-type flip-flops designed for 2-V to 5.5-V V

operation.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN − RGY Reel of 1000 SN74LV273ARGYR LV273A

SOIC − DW

Tube of 25 SN74LV273ADW LV273A

SOIC − DW

Reel of 2000 SN74LV273ADWR LV273A

SOP − NS Reel of 2000 SN74LV273ANSR 74LV273A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74LV273ADBR LV273A

−40 C to 85 C

Tube of 70 SN74LV273APW

TSSOP − PW

Reel of 2000 SN74LV273APWR

LV273A

TSSOP − PW

Reel of 250 SN74LV273APWT

LV273A

TVSOP − DGV Reel of 2000 SN74LV273ADGVR LV273A

CDIP − J Tube of 20 SNJ54LV273AJ SNJ54LV273AJ

−55°C to 125°C

CFP − W Tube of 85 SNJ54LV273AW SNJ54LV273AW

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54LV273AFK SNJ54LV273AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

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)&(&#$$(,

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (24 pages)

PAGE 1
SCLS399J − APRIL 1998 − REVISED APRIL 2005 D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down Mode Operation SN54LV273A . . . J OR W PACKAGE SN74LV273A . . .
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SCLS399J − APRIL 1998 − REVISED APRIL 2005 description/ordering information (continued) These devices are positive-edge-triggered flip-flops with direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse.
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SCLS399J − APRIL 1998 − REVISED APRIL 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
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SCLS399J − APRIL 1998 − REVISED APRIL 2005 recommended operating conditions (see Note 5) SN54LV273A VCC VIH High-level input voltage VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 2 5.5 Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 2 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 Output voltage UNIT V V 0.5 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 VCC × 0.
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SCLS399J − APRIL 1998 − REVISED APRIL 2005 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX CLR low tw Pulse duration tsu Setup time, data before CLK↑ th Hold time, data after CLK↑ CLK high or low Data CLR inactive SN54LV273A MIN MAX SN74LV273A MIN 6.5 7 7 7 8.5 8.5 8.5 10.5 10.5 4 4 4 0.
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SCLS399J − APRIL 1998 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd tPHL CLK CLR Q tpd tPHL CLK Q CLR Q TA = 25°C TYP MAX 75* 140* 65* 65 CL = 50 pF 50 110 45 45 CL = 15 pF CL = 50 pF fmax tpd tPHL tpd tPHL CLK Q CLR Q CLK Q MIN MAX MIN 1* 16* 1 16 6.9* 13.6* 1* 16* 1 16 9.1 17.
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SCLS399J − APRIL 1998 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC 50% VCC Input 50% VCC 0V th VCC 50% VCC Data Input 50% VC
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com (4) 18-Oct-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.5 2.5 12.0 16.0 Q1 SN74LV273ADBR SSOP DB 20 2000 330.0 16.4 SN74LV273ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV273ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV273ADBR SSOP DB 20 2000 367.0 367.0 38.0 SN74LV273ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74LV273ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LV273ANSR SO NS 20 2000 367.0 367.0 45.0 SN74LV273APWR TSSOP PW 20 2000 364.0 364.0 27.0 SN74LV273APWT TSSOP PW 20 250 367.0 367.0 38.
PAGE 13
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.