Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter NOR gate 74LV SOIC 14

 

   

SCES341E − SEPTEMBER 2000 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Max t

of 7 ns at 5 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2.3 V at V

= 3.3 V, T

= 25°C

D I

off

Supports Partial-Power-Down Mode

Operation

D Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

These triple 3-input positive-NOR gates are

designed for 2-V to 5.5-V V

operation.

The ’LV27A devices perform the Boolean function

Y = A + B + C

or Y = A • B • C in positive logic.

These devices are fully specified for

partial-power-down applications using I

off

. The I

off

circuitry disables the outputs, preventing

damaging current backflow through the devices

when they are powered down.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC − D

Tube of 50 SN74LV27AD

LV27A

SOIC − D

Reel of 2500 SN74LV27ADR

LV27A

SOP − NS Reel of 2000 SN74LV27ANSR 74LV27A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74LV27ADBR LV27A

−40°C to 85°C

Tube of 90 SN74LV27APW

TSSOP − PW

Reel of 2000 SN74LV27APWR

LV27A

TSSOP − PW

Reel of 250 SN74LV27APWT

LV27A

TVSOP − DGV Reel of 2000 SN74LV27ADGVR LV27A

CDIP − J Tube of 25 SNJ54LV27AJ SNJ54LV27AJ

−55°C to 125°C

CFP − W Tube of 150 SNJ54LV27AW SNJ54LV27AW

−55 C to 125 C

LCCC − FK Tube of 55 SNJ54LV27AFK SNJ54LV27AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

SN54LV27A ...FK PACKAGE

(TOP VIEW)

SN54LV27A ...J OR W PACKAGE

SN74LV27A ... D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

GND

NC − No internal connection

GND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

    !"# #$# %

 #&'!$# ''"# $ & ()*$# $"+ ' #&'! 

("&$# ("' " "'! & ",$ #'!"# $#$' -$''$#.+

'# ('"#/ " # #""$'*. #*" "#/ & $**

($'$!""'+

Summary of content (18 pages)

PAGE 1
SCES341E − SEPTEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP (Output Ground Bounce) D D D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.
PAGE 2
SCES341E − SEPTEMBER 2000 − REVISED APRIL 2005 FUNCTION TABLE (each gate) INPUTS A B C OUTPUT Y H X X L X H X L X X H L L L L H logic diagram, each gate (positive logic) A B C Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 3
SCES341E − SEPTEMBER 2000 − REVISED APRIL 2005 recommended operating conditions (see Note 4) SN54LV27A VCC VIH High-level input voltage VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 2 5.5 Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 2 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 Output voltage 0 0.5 0 VCC −50 VCC × 0.3 5.5 0 VCC −50 −2 VCC = 3 V to 3.
PAGE 4
SCES341E − SEPTEMBER 2000 − REVISED APRIL 2005 switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C TYP MAX PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tpd A, B, or C Y CL = 15 pF 6.7* tpd A, B, or C Y CL = 50 pF 9.5 MIN SN54LV27A SN74LV27A UNIT MIN MAX MIN MAX 13.8* 1* 16* 1 16 ns 17.
PAGE 5
SCES341E − SEPTEMBER 2000 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input 50% VCC th VCC 50% VCC Data Input 50% VCC 0
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LV27ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74LV27ADGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV27ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV27ADBR SSOP DB 14 2000 367.0 367.0 38.0 SN74LV27ADGVR TVSOP DGV 14 2000 367.0 367.0 35.0 SN74LV27ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LV27ANSR SO NS 14 2000 367.0 367.0 38.0 SN74LV27APWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74LV27APWT TSSOP PW 14 250 367.0 367.0 35.
PAGE 11
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 12
PAGE 13
PAGE 14
PAGE 15
PAGE 16
PAGE 17
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 18
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.