Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - analogue switches SOIC 14

SN54LV4066A, SN74LV4066A

QUADRUPLE BILATERAL ANALOG SWITCHES

SCLS427I − APRIL 1999 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Support Mixed-Mode Voltage Operation on

All Ports

D High On-Off Output-Voltage Ratio

D Low Crosstalk Between Switches

D Individual Switch Controls

D Extremely Low Input Current

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

This quadruple silicon-gate CMOS analog switch

is designed for 2-V to 5.5-V V

operation.

These switches are designed to handle both

analog and digital signals. Each switch permits

signals with amplitudes up to 5.5 V (peak) to be

transmitted in either direction.

Each switch section has its own enable-input

control (C). A high-level voltage applied to C turns

on the associated switch section.

Applications include signal gating, chopping,

modulation or demodulation (modem), and signal

multiplexing for analog-to-digital and

digital-to-analog conversion systems.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube of 25 SN74LV4066AN SN74LV4066AN

QFN − RGY Reel of 1000 SN74LV4066ARGYR LW066A

SOIC D

Tube of 50 SN74LV4066AD

LV4066A

SOIC − D

Reel of 2500 SN74LV4066ADR

LV4066A

40°Cto85°C

SOP − NS Reel of 2000 SN74LV4066ANSR 74LV4066A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74LV4066ADBR LW066A

Tube of 90 SN74LV4066APW

TSSOP − PW

Reel of 2000 SN74LV4066APWR

LW066A

TSSOP

Reel of 250 SN74LV4066APWT

LW066A

TVSOP − DGV Reel of 2000 SN74LV4066ADGVR LW066A

55°C to 125°C

CDIP − J Tube of 25 SNJ54LV4066AJ SNJ54LV4066AJ

−55°C to 125°C

CFP − W Tube of 150 SNJ54LV4066AW SNJ54LV4066AW

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

GND

SN54LV4066A ...J OR W PACKAGE

SN74LV4066A ...D, DB, DGV, N, NS, OR PW PACKAGE

(TOP VIEW)

SN74LV4066A . . . RGY PACKAGE

(TOP VIEW)

114

GND

NC − No internal connection

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Summary of content (27 pages)

PAGE 1
SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427I − APRIL 1999 − REVISED APRIL 2005 1A 1B 2B 2A 2C 3C GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 4C 4A 4B 3B 3A SN74LV4066A . . . RGY PACKAGE (TOP VIEW) description/ordering information This quadruple silicon-gate CMOS analog switch is designed for 2-V to 5.5-V VCC operation. 1B 2B 2A 2C 3C These switches are designed to handle both analog and digital signals. Each switch permits signals with amplitudes up to 5.
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SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427I − APRIL 1999 − REVISED APRIL 2005 FUNCTION TABLE (each switch) INPUT CONTROL (C) SWITCH L OFF H ON logic diagram (positive logic) A VCC VCC B C One of Four Switches absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
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SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427I − APRIL 1999 − REVISED APRIL 2005 recommended operating conditions (see Note 5) VCC Supply voltage VCC = 2 V VIH High level input voltage, High-level voltage control inputs SN54LV4066A SN74LV4066A MIN MAX MIN MAX 2† 5.5 2† 5.5 1.5 VIL Low level input voltage, Low-level voltage control inputs VI Control input voltage VCC × 0.7 VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.
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SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427I − APRIL 1999 − REVISED APRIL 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C MIN MAX MIN MAX SN74LV4066A MIN MAX UNIT IT = −1 mA,, VI = VCC or GND, VC = VIH (see Figure 1) 2.3 V 38 180 225 225 3V 29 150 190 190 4.5 V 21 75 100 100 IT = −1 mA, VI = VCC to GND, VC = VIH 2.
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SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427I − APRIL 1999 − REVISED APRIL 2005 switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS TA = 25°C MIN SN54LV4066A TYP MAX MIN MAX SN74LV4066A MIN MAX UNIT tPLH tPHL Propagation delay time A or B B or A CL = 15 pF, (see Figure 4) 1.
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SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427I − APRIL 1999 − REVISED APRIL 2005 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS TA = 25°C MIN SN54LV4066A TYP MAX MIN SN74LV4066A MAX MIN MAX UNIT tPLH tPHL Propagation delay time A or B B or A CL = 15 pF, (see Figure 4) 0.
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SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427I − APRIL 1999 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VCC VC = VIH VCC VI = VCC or GND VO (ON) GND r on + VI – VO 10 –3 W 1 mA V VI − VO Figure 1. On-State Resistance Test Circuit VCC VC = VIL VCC VI A (OFF) VO GND Condition 1: VI = 0, VO = VCC Condition 2: VI = VCC, VO = 0 Figure 2. Off-State Switch Leakage-Current Test Circuit VCC VC = VIH VCC VI A (ON) Open GND VI = VCC or GND Figure 3.
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SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427I − APRIL 1999 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VCC VC = VIH VCC VI VO (ON) 50 Ω CL GND TEST CIRCUIT tr VI A or B tf 90% 50% 10% VCC 90% 50% 10% tPLH 0V tPHL VOH VO B or A 50% 50% VOL VOLTAGE WAVEFORMS Figure 4.
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SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427I − APRIL 1999 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VCC 50 Ω VC VCC VI S1 VO RL = 1 kΩ TEST S1 S2 tPZL tPZH tPLZ tPHZ GND VCC GND VCC VCC GND VCC GND S2 CL GND TEST CIRCUIT VCC VC VCC 50% 50% 0V 0V tPZL tPZH ≈VCC VO VOL VOH 50% 50% ≈0 V (tPZL, tPZH) VCC VC VCC 50% 50% 0V 0V tPLZ tPHZ ≈VCC VO VOL VOH VOL + 0.3 V VOH − 0.3 V ≈0 V (tPLZ, tPHZ) VOLTAGE WAVEFORMS Figure 5.
PAGE 10
SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427I − APRIL 1999 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VCC VCC 0.1 μF fin VCC VI VO (ON) GND 50 Ω RL = 600 Ω CL = 50 pF VCC/2 Figure 6. Frequency Response (Switch On) VCC VC = VCC 50 Ω VCC VI fin VO1 (ON) 0.1 μF 600 Ω GND CL = 50 pF RL = 600 Ω VCC/2 VI VCC VC = GND VCC (OFF) 600 Ω VO2 GND RL = 600 Ω CL = 50 pF VCC/2 Figure 7.
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SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427I − APRIL 1999 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VCC VC = GND 0.1 μF fin 50 Ω VI VCC VO (OFF) GND 600 Ω RL = 600 Ω CL = 50 pF VCC/2 VCC/2 Figure 9. Feed-Through Attenuation (Switch Off) VCC VC = VCC 10 μF fin 600 Ω VI 10 μF VCC VO (ON) GND RL = 10 kΩ CL = 50 pF VCC/2 Figure 10.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.com 22-Dec-2009 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LV4066ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74LV4066ARGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LV4066ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74LV4066ADGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV4066ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV4066ADBR SSOP DB 14 2000 367.0 367.0 38.0 SN74LV4066ADGVR TVSOP DGV 14 2000 367.0 367.0 35.0 SN74LV4066ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LV4066ANSR SO NS 14 2000 367.0 367.0 38.0 SN74LV4066APWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74LV4066APWT TSSOP PW 14 250 367.0 367.0 35.
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.