Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Standard Three-state, Non-inverting SOIC 20

SN54LV574A, SN74LV574A

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCLS412I − APRIL 1998 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Max t

of 10 ns at 5 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2.3 V at V

= 3.3 V, T

= 25°C

D Support Mixed-Mode Voltage Operation on

All Ports

D I

off

Supports Partial-Power-Down Mode

Operation

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

SN54LV574A . . . FK PACKAGE

(TOP VIEW)

SN54LV574A ...J OR W PACKAGE

SN74LV574A . . . DB, DGV, DW, NS,

OR PW PACKAGE

(TOP VIEW)

GND

CLK

3212019

910111213

7Q 1Q

GND

CLK

SN74LV574A . . . RGY PACKAGE

(TOP VIEW)

120

10 11

CLK

GND

description/ordering information

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN − RGY Reel of 1000 SN74LV574ARGYR LV574A

SOIC DW

Tube of 25 SN74LV574ADW

LV574A

SOIC − DW

Reel of 2000 SN74LV574ADWR

LV574A

SOP − NS Reel of 2000 SN74LV574ANSR 74LV574A

40°Cto85°C

SSOP − DB Reel of 2000 SN74LV574ADBR LV574A

−40°C to 85°C

Tube of 70 SN74LV574APW

TSSOP − PW

Reel of 2000 SN74LV574APWR

LV574A

TSSOP

Reel of 250 SN74LV574APWT

LV574A

TVSOP − DGV Reel of 2000 SN74LV574ADGVR LV574A

VFBGA − GQN Reel of 1000 SN74LV574AGQNR LV574A

CDIP − J Tube of 20 SNJ54LV574AJ SNJ54LV574AJ

−55°C to 125°C

CFP − W Tube of 85 SNJ54LV574AW SNJ54LV574AW

LCCC − FK Tube of 55 SNJ54LV574AFK SNJ54LV574AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (23 pages)

PAGE 1
SN54LV574A, SN74LV574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS412I − APRIL 1998 − REVISED APRIL 2005 2 19 3 18 17 4 16 5 15 6 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK 1D 2D 3D 4D 5D 6D 7D 8D 1 20 19 1Q 18 2Q 2 3 17 3Q 16 4Q 4 5 15 5Q 14 6Q 6 7 SN54LV574A . . . FK PACKAGE (TOP VIEW) 2D 1D OE VCC VCC 20 1 SN74LV574A . . .
PAGE 2
SN54LV574A, SN74LV574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS412I − APRIL 1998 − REVISED APRIL 2005 description/ordering information (continued) The ’LV574A devices are octal edge-triggered D-type flip-flops designed for 2-V to 5.5-V VCC operation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads.
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SN54LV574A, SN74LV574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS412I − APRIL 1998 − REVISED APRIL 2005 logic diagram (positive logic) OE CLK 1 11 C1 1D 2 19 1Q 1D To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, FK, J, NS, PW, RGY, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SN54LV574A, SN74LV574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS412I − APRIL 1998 − REVISED APRIL 2005 recommended operating conditions (see Note 5) VCC SN54LV574A SN74LV574A MIN MAX MIN MAX 2 5.5 2 5.5 Supply voltage VCC = 2 V VIH High level input voltage High-level 1.5 Low level input voltage Low-level VI Input voltage VO Output voltage VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.
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SN54LV574A, SN74LV574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS412I − APRIL 1998 − REVISED APRIL 2005 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C PARAMETER MIN tw Pulse duration CLK high or low tsu Setup time High or low before CLK↑ th Hold time Data after CLK↑ SN54LV574A MAX MIN MAX SN74LV574A MIN MAX UNIT 7 7 7 ns 5.5 5.5 5.
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SN54LV574A, SN74LV574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS412I − APRIL 1998 − REVISED APRIL 2005 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.
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SN54LV574A, SN74LV574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS412I − APRIL 1998 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) S1 Open TEST GND S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain CL (see Note A) Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 26-Aug-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.5 2.5 12.0 16.0 Q1 SN74LV574ADBR SSOP DB 20 2000 330.0 16.4 SN74LV574ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV574ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV574ADBR SSOP DB 20 2000 367.0 367.0 38.0 SN74LV574ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74LV574ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LV574ANSR SO NS 20 2000 367.0 367.0 45.0 SN74LV574APWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74LV574APWT TSSOP PW 20 250 367.0 367.0 38.
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.