Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Shift register Shift register Three-state SOIC 16 N

SN54LV595A, SN74LV595A

8-BIT SHIFT REGISTERS

WITH 3-STATE OUTPUT REGISTERS

SCLS414O − APRIL 1998 − REVISED JANUARY 2011

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Max t

of 7.1 ns at 5 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2.3 V at V

= 3.3 V, T

= 25°C

D Support Mixed-Mode Voltage Operation on

All Ports

D 8-Bit Serial-In, Parallel-Out Shift

D I

off

Supports Partial-Power-Down Mode

Operation

D Shift Register Has Direct Clear

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

SN54LV595A ...J OR W PACKAGE

SN74LV595A . . . D, DB, NS,

OR PW PACKAGE

(TOP VIEW)

SN54LV595A . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

GND

SER

RCLK

SRCLK

SRCLR

′

3212019

910111213

SER

RCLK

SRCLK

SRCLR

GND

′

SN74LV595A . . . RGY PACKAGE

(TOP VIEW)

116

SER

RCLK

SRCLK

SRCLR

GND

H′

description/ordering information

The ’LV595A devices are 8-bit shift registers designed for 2-V to 5.5-V V

operation.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN − RGY Reel of 1000 SN74LV595ARGYR LV595A

SOIC D

Tube of 40 SN74LV595ADG3

LV595A

SOIC − D

Reel of 2500 SN74LV595ADR

LV595A

40°C to 85°C

SOP − NS Reel of 2000 SN74LV595ANSR 74LV595A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74LV595ADBR LV595A

Tube of 90 SN74LV595APW

TSSOP − PW

Reel of 2000 SN74LV595APWRG3

LV595A

TSSOP PW

Reel of 250 SN74LV595APWT

LV595A

CDIP − J Tube of 25 SNJ54LV595AJ SNJ54LV595AJ

−55°C to 125°C

CFP − W Tube of 150 SNJ54LV595AW SNJ54LV595AW

LCCC − FK Tube of 55 SNJ54LV595AFK SNJ54LV595AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (26 pages)

PAGE 1
SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O − APRIL 1998 − REVISED JANUARY 2011 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER OE RCLK SRCLK SRCLR QH′ QC QD QE QF QG QH 16 QC QB 1 15 2 3 14 4 13 5 12 6 11 7 10 8 9 QD QE NC QF QG QA SER OE RCLK SRCLK SRCLR 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 SER OE NC RCLK SRCLK SRCLR 16 GND NC QH ′ 1 SN54LV595A . . .
PAGE 2
SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O − APRIL 1998 − REVISED JANUARY 2011 description/ordering information (continued) These devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register.
PAGE 3
SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O − APRIL 1998 − REVISED JANUARY 2011 logic diagram (positive logic) OE RCLK SRCLR SRCLK SER 13 12 10 11 14 1D Q C1 R 3D C3 Q 15 2D Q C2 R 3D C3 Q 1 2D Q C2 R 3D C3 Q 2 2D Q C2 R 3D C3 Q 3 2D Q C2 R 3D C3 Q 4 2D Q C2 R 3D C3 Q 5 2D Q C2 R 3D C3 Q 6 2D Q C2 R 3D C3 Q 7 9 QA QB QC QD QE QF QG QH QH′ Pin numbers shown are for the D, DB, J, NS, PW, RGY, and W packages.
PAGE 4
SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O − APRIL 1998 − REVISED JANUARY 2011 timing diagram SRCLK SER RCLK SRCLR OE ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ QA QB QC QD QE QF QG QH QH′ NOTE: 4 ÎÎÎÎ implies that the output is in 3-State mode.
PAGE 5
SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O − APRIL 1998 − REVISED JANUARY 2011 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 6
SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O − APRIL 1998 − REVISED JANUARY 2011 recommended operating conditions (see Note 5) SN54LV595A VCC Supply voltage VCC = 2 V VIH High level input voltage High-level MIN MAX 2 5.5 1.5 Low level input voltage Low-level VI Input voltage VO Output voltage VCC × 0.7 VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7 Δt/Δv Input transition rise or fall rate 0.5 TA 0.5 VCC × 0.3 VCC × 0.3 VCC = 3 V to 3.
PAGE 7
SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O − APRIL 1998 − REVISED JANUARY 2011 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS SN54LV595A VCC MIN IOH = −50 μA 2 V to 5.5 V IOH = −2 mA 2.3 V QH′ IOH = −6 mA QA−QH IOH = −8 mA QH′ IOH = −12 mA QA−QH IOH = −16 mA TYP SN74LV595A MAX VCC−0.1 3V 45V 4.5 MIN TYP MAX VCC−0.1 2 2 2.48 2.48 2.48 2.48 3.
PAGE 8
SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O − APRIL 1998 − REVISED JANUARY 2011 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN tw Pulse duration th Hold time MAX SN74LV595A MIN 5.5 5.5 5.5 5.5 5.5 5.5 5 5 5 3.5 3.5 3.5 SRCLK↑ before RCLK↑† 8 8.5 8.
PAGE 9
SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O − APRIL 1998 − REVISED JANUARY 2011 switching characteristics over recommended operating VCC = 2.5 V ± 0.
PAGE 10
SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O − APRIL 1998 − REVISED JANUARY 2011 switching characteristics over recommended operating VCC = 3.3 V ± 0.
PAGE 11
SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O − APRIL 1998 − REVISED JANUARY 2011 switching characteristics over recommended operating VCC = 5 V ± 0.
PAGE 12
SN54LV595A, SN74LV595A 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS SCLS414O − APRIL 1998 − REVISED JANUARY 2011 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) S1 VCC Open TEST GND CL (see Note A) tw 50% VCC 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC tPLH In-Phase Output tPHL Out-of-Phase Output 0V VCC Output Control 50% VCC tPHL 50% VCC tPZL VOH 50% VCC VOL tPLH VOH 50% VCC 50% VCC 0V VOLTAGE W
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LV595ADR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV595ADRG3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV595ADRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
PAGE 17
PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV595ADR SOIC D 16 2500 364.0 364.0 27.0 SN74LV595ADRG3 SOIC D 16 2500 364.0 364.0 27.0 SN74LV595ADRG4 SOIC D 16 2500 333.2 345.9 28.6 SN74LV595ANSR SO NS 16 2000 367.0 367.0 38.0 SN74LV595APWR TSSOP PW 16 2000 364.0 364.0 27.0 SN74LV595APWRG3 TSSOP PW 16 2000 364.0 364.0 27.
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