Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Shift register Shift register Three-state TSSOP 16

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  

   

SCLS568B − JANUARY 2004 − REVISED MAY 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

D Enhanced Diminishing Manufacturing

Sources (DMS) Support

D Enhanced Product-Change Notification

D Qualification Pedigree

†

D 2-V to 5.5-V V

Operation

D Max t

of 7.4 ns at 5 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2.3 V at V

= 3.3 V, T

= 25°C

†

Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

D Supports Mixed-Mode Voltage Operation on

All Ports

D 8-Bit Serial-In, Parallel-Out Shift

D I

off

Supports Partial-Power-Down Mode

Operation

D Shift Register Has Direct Clear

description/ordering information

The SN74LV595A is an 8-bit shift register designed for 2-V to 5.5-V V

operation.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The

storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register.

The shift register has a direct overriding clear (SRCLR

) input, serial (SER) input, and a serial output for

cascading. When the output-enable (OE

) input is high, all outputs except Q

H′

are in the high-impedance state.

Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both

clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

To ensure the high-impedance state during power up or power down, OE

should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

PACKAGE

‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−40°C to 85°C TSSOP − PW Reel of 2000 SN74LV595AIPWREP LV595EP

‡

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PW PACKAGE

(TOP VIEW)

GND

SER

RCLK

SRCLK

SRCLR

H′

Summary of content (17 pages)

PAGE 1
SCLS568B − JANUARY 2004 − REVISED MAY 2004 D Controlled Baseline D D D D D D D D Supports Mixed-Mode Voltage Operation on − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† 2-V to 5.5-V VCC Operation Max tpd of 7.4 ns at 5 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.
PAGE 2
SCLS568B − JANUARY 2004 − REVISED MAY 2004 FUNCTION TABLE INPUTS 2 SER SRCLK X X X X X X L SRCLR FUNCTION RCLK OE X X H X X L Outputs QA−QH are disabled. Outputs QA−QH are enabled. L X X Shift register is cleared. ↑ H X X First stage of the shift register goes low. Other stages store the data of previous stage, respectively. H ↑ H X X First stage of the shift register goes high.
PAGE 3
SCLS568B − JANUARY 2004 − REVISED MAY 2004 logic diagram (positive logic) OE RCLK SRCLR SRCLK SER 13 12 10 11 14 1D Q C1 R 3D C3 Q 15 2D Q C2 R 3D C3 Q 1 2D Q C2 R 3D C3 Q 2 2D Q C2 R 3D C3 Q 3 2D Q C2 R 3D C3 Q 4 2D Q C2 R 3D C3 Q 5 2D Q C2 R 3D C3 Q 6 2D Q C2 R 3D C3 Q 7 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 QA QB QC QD QE QF QG QH QH′ 3
PAGE 4
SCLS568B − JANUARY 2004 − REVISED MAY 2004 timing diagram SRCLK SER RCLK SRCLR OE ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ QA QB QC QD QE QF QG QH QH′ 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PAGE 5
SCLS568B − JANUARY 2004 − REVISED MAY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 6
SCLS568B − JANUARY 2004 − REVISED MAY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −50 µA IOH = −2 mA VOH QH′ QA−QH QH′ QA−QH 2 V to 5.5 V 2.3 V IOH = −6 mA IOH = −8 mA QH′ QA−QH QH′ QA−QH 3.8 VI = VCC or GND, VI or VO = 0 to 5.5 V Ci VI = VCC or GND 3.8 2 V to 5.5 V 0.1 2.3 V 0.4 0.44 3V IOL = 12 mA IOL = 16 mA ICC Ioff UNIT V 2.
PAGE 7
SCLS568B − JANUARY 2004 − REVISED MAY 2004 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration SRCLK high or low 5.5 5.5 RCLK high or low 5.5 5.5 5 5 SRCLR low SER before SRCLK↑ tsu Setup time MIN 3.5 3.5 SRCLK↑ before RCLK↑† 8 8.
PAGE 8
SCLS568B − JANUARY 2004 − REVISED MAY 2004 switching characteristics over recommended operating VCC = 2.5 V ± 0.
PAGE 9
SCLS568B − JANUARY 2004 − REVISED MAY 2004 switching characteristics over recommended operating VCC = 3.3 V ± 0.
PAGE 10
SCLS568B − JANUARY 2004 − REVISED MAY 2004 switching characteristics over recommended operating VCC = 5 V ± 0.
PAGE 11
SCLS568B − JANUARY 2004 − REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input 50% VCC th VCC 50% VCC Data Input
PAGE 12
PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LV595AIPWREP ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04696-01XE ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LV595AIPWREP Package Package Pins Type Drawing TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV595AIPWREP TSSOP PW 16 2000 367.0 367.0 35.
PAGE 15
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.