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SCES610 − OCTOBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Max t

of 15 ns at 5 V

D Schmitt-Trigger Inputs Allow for Slow Input

Rise/Fall Time

D Polarity Control for Y Outputs Selects True

or Complementary Logic

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2.3 V at V

= 3.3 V, T

= 25°C

D I

off

Supports Partial-Power-Down Mode

Operation

D Supports Mixed-Mode Voltage Operation on

All Ports

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

The SN74LV8151 is a 10-bit universal Schmitt-trigger buffer with 3-state outputs, designed for 2-V to 5.5-V V

operation. The logic control (T/C) pin allows the user to configure Y1 to Y8 as noninverting or inverting outputs.

When T/C

is high, the Y outputs are noninverted (true logic ), and when T/C is low, the Y outputs are inverted

(complementary logic).

When output-enable (OE

) input is low, the device passes data from Dn to Yn. When OE is high, the Y outputs

are in the high-impedance state. The path A to P is a simple Schmitt-trigger buffer, and the path B to N is a simple

Schmitt-trigger inverter.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE

should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − NT Tube SN74LV8151NT SN74LV8151NT

−40°C to 85°C

TSSOP − PW

Tube SN74LV8151PW

LV8151

−40 C to 85 C

TSSOP − PW

Tape and reel SN74LV8151PWR

LV8151

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

NT OR PW PACKAGE

(TOP VIEW)

T/C

GND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (18 pages)

PAGE 1
SCES610 − OCTOBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 15 ns at 5 V D Schmitt-Trigger Inputs Allow for Slow Input D D D D D D D NT OR PW PACKAGE (TOP VIEW) T/C A B D1 D2 D3 D4 D5 D6 D7 D8 GND Rise/Fall Time Polarity Control for Y Outputs Selects True or Complementary Logic Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.
PAGE 2
SCES610 − OCTOBER 2004 FUNCTION TABLES INPUT A OUTPUT P L L H H INPUT B OUTPUT N L H H L INPUTS D OUTPUT Y L L H L H L L H L L L H H H H X X Z OE T/C L L logic diagram A B T/C D1 2 23 3 22 1 13 4 21 To Seven Other Channels 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P N OE Y1
PAGE 3
SCES610 − OCTOBER 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 4
SCES610 − OCTOBER 2004 recommended operating conditions (see Note 5) VCC VCC MIN MAX 2 5.5 2V 1.5 Supply voltage 3 V to 3.6 V VCC × 0.7 VCC × 0.7 4.5 V to 5.5 V VCC × 0.7 2.3 V to 2.
PAGE 5
SCES610 − OCTOBER 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VT+ Positive-going input threshold voltage VT− Negative-going input threshold voltage ∆VT Hysteresis (VT+ − VT−) TEST CONDITIONS A, B, and D inputs A, B, and D inputs A, B, and D inputs IOL = 50 µA IOL = 2 mA 1.75 3.3 V 2.31 II IOZ VI = 5.
PAGE 6
SCES610 − OCTOBER 2004 switching characteristics over recommended operating VCC = 3.3 V ± 0.
PAGE 7
SCES610 − OCTOBER 2004 operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance CL = No load, f = 1 MHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC 3.
PAGE 8
SCES610 − OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain CL (see Note A) CL (see Note A) Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LV8151DGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV8151DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV8151DGVR TVSOP DGV 24 2000 367.0 367.0 35.0 SN74LV8151DWR SOIC DW 24 2000 367.0 367.0 45.
PAGE 13
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.