Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74LVC TSSOP 14

www.ti.com

FEATURES

GND

SN54LVC00A . . . J OR W PACKAGE

SN74LVC00A . . . D, DB, NS, OR PW PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

GND

SN54LVC00A . . . FK PACKAGE

(TOP VIEW)

NC - No internal connection

SN74LVC00A . . . RGY PACKAGE

(TOP VIEW)

1 14

7 8

GND

DESCRIPTION/ORDERING INFORMATION

SN54LVC00A, SN74LVC00A

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SCAS279P – JANUARY 1993 – REVISED JULY 2005

• Operate From 1.65 V to 3.6 V • Latch-Up Performance Exceeds 250 mA Per

JESD 17

• Specified From –40 ° C to 85 ° C, –40 ° C to 125 ° C,

and –55 ° C to 125 ° C • ESD Protection Exceeds JESD 22

• Inputs Accept Voltages to 5.5 V – 2000-V Human-Body Model (A114-A)

• Max t

of 4.3 ns at 3.3 V – 200-V Machine Model (A115-A)

• Typical V

OLP

(Output Ground Bounce) – 1000-V Charged-Device Model (C101)

<0.8 V at V

= 3.3 V, T

= 25 ° C xxxxxx

xxxxxx

• Typical V

OHV

(Output V

Undershoot)

>2 V at V

= 3.3 V, T

= 25 ° C

The SN54LVC00A quadruple 2-input positive-NAND gate is designed for 2.7-V to 3.6-V V

operation, and the

SN74LVC00A quadruple 2-input positive-NAND gate is designed for 1.65-V to 3.6-V V

operation.

The 'LVC00A devices perform the Boolean function Y = A • B or Y = A + B in positive logic.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

On products compliant to MIL-PRF-38535, all parameters are

Instruments standard warranty. Production processing does not

tested unless otherwise noted. On all other products, production

necessarily include testing of all parameters.

processing does not necessarily include testing of all parameters.

Summary of content (26 pages)

PAGE 1
SN54LVC00A, SN74LVC00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES www.ti.com SCAS279P – JANUARY 1993 – REVISED JULY 2005 FEATURES 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 1 14 2 13 4B 3 4 12 4A 11 4Y 10 3B 5 6 9 3A 7 8 SN54LVC00A . . . FK PACKAGE (TOP VIEW) 1B 1A NC VCC 4B SN74LVC00A . . .
PAGE 2
SN54LVC00A, SN74LVC00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES www.ti.
PAGE 3
SN54LVC00A, SN74LVC00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES www.ti.com SCAS279P – JANUARY 1993 – REVISED JULY 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 VCC + 0.
PAGE 4
SN54LVC00A, SN74LVC00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES www.ti.com SCAS279P – JANUARY 1993 – REVISED JULY 2005 Recommended Operating Conditions (1) SN54LVC00A –55°C to 125°C Supply voltage VIH High-level input voltage VCC = 2.7 V to 3.6 V VIL Low-level input voltage VCC = 2.7 V to 3.6 V VI Input voltage VO Output voltage Data retention only IOH High-level output current IOL Low-level output current (1) MAX 2 3.6 Operating VCC UNIT MIN V 1.5 2 V 0.8 V 0 5.
PAGE 5
SN54LVC00A, SN74LVC00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES www.ti.com SCAS279P – JANUARY 1993 – REVISED JULY 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LVC00A PARAMETER TEST CONDITIONS VCC –55°C to 125°C UNIT MIN MAX IOH = –100 µA VOH VOL 2.7 V to 3.6 V 2.2 3V 2.4 IOH = –24 mA 3V 2.2 IOL = 100 µA 2.7 V to 3.6 V 0.2 IOL = 12 mA 2.7 V 0.4 3V 0.55 IOH = –12 mA IOL = 24 mA II ICC ∆ICC VCC – 0.2 2.
PAGE 6
SN54LVC00A, SN74LVC00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES www.ti.com SCAS279P – JANUARY 1993 – REVISED JULY 2005 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVC00A FROM (INPUT) PARAMETER TO (OUTPUT) VCC –55°C to 125°C MIN tpd A or B 2.7 V Y UNIT MAX 5.1 3.3 V ± 0.3 V 1 4.
PAGE 7
SN54LVC00A, SN74LVC00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES www.ti.com SCAS279P – JANUARY 1993 – REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVC00ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74LVC00ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LVC00ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC00ADBR SSOP DB 14 2000 367.0 367.0 38.0 SN74LVC00ADR SOIC D 14 2500 333.2 345.9 28.6 SN74LVC00ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LVC00ADT SOIC D 14 250 367.0 367.0 38.0 SN74LVC00ANSR SO NS 14 2000 367.0 367.0 38.0 SN74LVC00APWR TSSOP PW 14 2000 364.0 364.0 27.
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 19
PAGE 20
PAGE 21
PAGE 22
PAGE 23
PAGE 24
PAGE 25
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 26
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.