Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state TSSOP 48

www.ti.com

FEATURES

DESCRIPTION/ORDERING INFORMATION

1OE

1Q1

1Q2

GND

1Q3

1Q4

1Q5

1Q6

GND

1Q7

1Q8

2Q1

2Q2

GND

2Q3

2Q4

2Q5

2Q6

GND

2Q7

2Q8

2OE

1LE

1D1

1D2

GND

1D3

1D4

1D5

1D6

GND

1D7

1D8

2D1

2D2

GND

2D3

2D4

2D5

2D6

GND

2D7

2D8

2LE

DGG, DGV, OR DL PACKAGE

(TOP VIEW)

SN74LVC16373A

16-BIT TRANSPARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS

SCAS755A – DECEMBER 2003 – REVISED SEPTEMBER 2005

• Member of the Texas Instruments Widebus™

Family

• Operates From 1.65 V to 3.6 V

• Inputs Accept Voltages to 5.5 V

• Max t

of 4.2 ns at 3.3 V

• Typical V

OLP

(Output Ground Bounce) <0.8 V

at V

= 3.3 V, T

= 25 ° C

• Typical V

OHV

(Output V

Undershoot) >2 V

at V

= 3.3 V, T

= 25 ° C

• I

off

Supports Partial-Power-Down Mode

Operation

• Supports Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V V

)

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 1000-V Charged-Device Model (C101)

This 16-bit transparent D-type latch is designed for

1.65-V to 3.6-V V

operation.

The SN74LVC16373A is particularly suitable for

implementing buffer registers, I/O ports, bidirectional

bus drivers, and working registers. The device can be

used as two 8-bit latches or one 16-bit latch. When

the latch-enable (LE) input is high, the Q outputs

follow the data (D) inputs. When LE is taken low, the

Q outputs are latched at the levels set up at the D

inputs.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

FBGA – GRD SN74LVC16373AGRDR

Tape and reel LD373A

FBGA – ZRD (Pb-free) SN74LVC16373AZRDR

Tube SN74LVC16373ADL

SSOP – DL LVC16373A

Tape and reel SN74LVC16373ADLR

SN74LVC16373ADGGR

–40 ° C to 85 ° C TSSOP – DGG Tape and reel LVC16373A

74LVC16373ADGGRG4

SN74LVC16373ADGVR

TVSOP – DGV Tape and reel LD373A

74LVC16373ADGVRE4

VFBGA – GQL SN74LVC16373AGQLR

Tape and reel LD373A

VFBGA – ZQL (Pb-free) SN74LVC16373AZQLR

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (17 pages)

PAGE 1
SN74LVC16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS755A – DECEMBER 2003 – REVISED SEPTEMBER 2005 FEATURES • • • • • • • • • • DGG, DGV, OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus™ Family Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.2 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.
PAGE 2
SN74LVC16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS755A – DECEMBER 2003 – REVISED SEPTEMBER 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
PAGE 3
SN74LVC16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS755A – DECEMBER 2003 – REVISED SEPTEMBER 2005 FUNCTION TABLE INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1LE 1 2OE 48 2LE C1 1D1 47 2 1D 24 25 C1 1Q1 2D1 36 To Seven Other Channels 13 1D 2Q1 To Seven Other Channels Pin numbers shown are for the DGG, DGV, and DL packages.
PAGE 4
SN74LVC16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS755A – DECEMBER 2003 – REVISED SEPTEMBER 2005 Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VIH High-level input voltage MIN MAX 1.65 3.6 1.5 Low-level input voltage VI VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 VO Output voltage IOH High-level output current 0.35 × VCC 0.7 VCC = 2.7 V to 3.6 V 0.8 0 5.
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SN74LVC16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS755A – DECEMBER 2003 – REVISED SEPTEMBER 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –100 µA VOH 1.65 V to 3.6 V 1.2 IOH = –8 mA 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = –24 mA 3V 2.2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.7 IOL = 12 mA 2.7 V 0.4 3V 0.55 V V 3.
PAGE 6
SN74LVC16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS755A – DECEMBER 2003 – REVISED SEPTEMBER 2005 Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER Cpd 6 Power dissipation capacitance per latch Outputs enabled Outputs disabled f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.
PAGE 7
SN74LVC16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS755A – DECEMBER 2003 – REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 13-Dec-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.6 15.8 1.8 12.0 24.0 Q1 SN74LVC16373ADGGR TSSOP DGG 48 2000 330.0 24.4 SN74LVC16373ADGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1 SN74LVC16373ADLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 13-Dec-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC16373ADGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74LVC16373ADGVR TVSOP DGV 48 2000 367.0 367.0 38.0 SN74LVC16373ADLR SSOP DL 48 1000 367.0 367.0 55.0 SN74LVC16373AZQLR BGA MICROSTAR JUNIOR ZQL 56 1000 333.2 345.9 28.6 SN74LVC16373AZRDR BGA MICROSTAR JUNIOR ZRD 54 1000 333.2 345.9 28.
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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 17
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.