Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74LVC SOT 23 5

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FEATURES

DBV OR DCK PACKAGE

(TOP VIEW)

GND

DESCRIPTION/ORDERING INFORMATION

SN74LVC1G00-EP

SINGLE 2-INPUT POSITIVE-NAND GATE

SCES450D – DECEMBER 2003 – REVISED SEPTEMBER 2006

• Controlled Baseline • I

off

Supports Partial-Power-Down Mode

Operation

– One Assembly/Test Site, One Fabrication

Site • Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• Enhanced Diminishing Manufacturing

Sources (DMS) Support • ESD Protection Exceeds JESD 22

• Enhanced Product-Change Notification – 2000-V Human-Body Model (A114-A)

• Qualification Pedigree

(1)

– 200-V Machine Model (A115-A)

• Supports 5-V V

Operation – 1000-V Charged-Device Model (C101)

• Inputs Accept Voltages to 5.5 V

• Max t

of 3.8 ns at 3.3 V

• Low Power Consumption, 10- µ A Max I

• ± 24-mA Output Drive at 3.3 V

(1) Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V V

operation.

The SN74LVC1G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

(2)

–40 ° C to 85 ° C SOP (SC-70) – DCK Reel of 3000 SN74LVC1G00IDCKREP CAO

SOP – DBV Reel of 3000 SN74LVC1G00MDBVREP SBFM

–55 ° C to 125 ° C

SOP (SC-70) – DCK Reel of 3000 SN74LVC1G00MDCKREP BYA

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) The actual top-side marking has one additional character that designates the assembly/test site.

FUNCTION TABLE

INPUTS

OUTPUT

A B

H H L

L X H

X L H

LOGIC DIAGRAM (POSITIVE LOGIC)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (15 pages)

PAGE 1
SN74LVC1G00-EP SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES450D – DECEMBER 2003 – REVISED SEPTEMBER 2006 FEATURES • • • • • • • • • (1) • Controlled Baseline – One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 3.8 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.
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SN74LVC1G00-EP SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES450D – DECEMBER 2003 – REVISED SEPTEMBER 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.
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SN74LVC1G00-EP SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES450D – DECEMBER 2003 – REVISED SEPTEMBER 2006 Recommended Operating Conditions VCC Supply voltage (1) Operating Data retention only High-level input voltage MAX 1.65 5.5 1.5 VCC = 2.3 V to 2.7 V 1.7 VCC = 3 V to 3.6 V 0.7 × VCC 0.35 × VCC VCC = 1.65 V to 1.95 V Low-level input voltage V V 2 VCC = 4.5 V to 5.5 V VIL UNIT 0.65 × VCC VCC = 1.65 V to 1.95 V VIH MIN VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 V 0.
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SN74LVC1G00-EP SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES450D – DECEMBER 2003 – REVISED SEPTEMBER 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –100 µA VOH 1.65 V to 5.5 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.9 4.5 V 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 0.4 ICC VI = 5.5 V or GND, IO = 0 ∆ICC One input at VCC – 0.
PAGE 5
SN74LVC1G00-EP SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES450D – DECEMBER 2003 – REVISED SEPTEMBER 2006 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.
PAGE 6
SN74LVC1G00-EP SINGLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCES450D – DECEMBER 2003 – REVISED SEPTEMBER 2006 PARAMETER MEASUREMENT INFORMATION (continued) VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LVC1G00IDCKREP Package Package Pins Type Drawing SC70 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 SN74LVC1G00MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SN74LVC1G00MDCKREP DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G00IDCKREP SC70 DCK 5 3000 203.0 203.0 35.0 SN74LVC1G00MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0 SN74LVC1G00MDCKREP SC70 DCK 5 3000 203.0 203.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.