Datasheet

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FEATURES

DBV PACKAGE

(TOP VIEW)

GND

B Y

DCK PACKAGE

(TOP VIEW)

GND

YZP PACKAGE

(BOTTOM VIEW)

GND

DESCRIPTION/ORDERING INFORMATION

SN74LVC1G0832

SINGLE 3-INPUT POSITIVE AND-OR GATE

SCES606C – SEPTEMBER 2004 – REVISED JANUARY 2007

• Available in the Texas Instruments

NanoFree™ Package

• Supports 5-V V

Operation

• Inputs Accept Voltages to 5.5 V

• Max t

of 5 ns at 3.3 V

• Low Power Consumption, 10- µ A Max I

• ± 24-mA Output Drive at 3.3 V

• Input Hysteresis Allows Slow Input

Transition and Better Switching Noise

Immunity at the Input

hys

= 250 mV Typ @ 3.3 V)

• Can Be Used in Three Combinations:

– AND-OR Gate

– AND Gate

– OR Gate

• I

off

Supports Partial-Power-Down Mode

Operation

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

This device is designed for 1.65-V to 5.5-V V

operation.

The SN74LVC1G0832 is a single 3-input positive AND-OR gate. It performs the Boolean function Y = (A • B ) +

C in positive logic.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

(2)

NanoFree™ – WCSP (DSBGA)

Reel of 3000 SN74LVC1G0832YZPR _ _ _DC_

0.23-mm Large Bump – YZP (Pb-free)

Reel of 3000 SN74LVC1G0832DBVR

SOT (SOT-23) – DBV CDC_

–40 ° C to 85 ° C

Reel of 250 SN74LVC1G0832DBVT

Reel of 3000 SN74LVC1G0832DCKR

SOT (SC-70) – DCK DC_

Reel of 250 SN74LVC1G0832DCKT

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.

YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoFree is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (17 pages)

PAGE 1
SN74LVC1G0832 SINGLE 3-INPUT POSITIVE AND-OR GATE www.ti.com SCES606C – SEPTEMBER 2004 – REVISED JANUARY 2007 FEATURES • • • • • • • • • • • DBV PACKAGE (TOP VIEW) Available in the Texas Instruments NanoFree™ Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 5 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typ @ 3.
PAGE 2
SN74LVC1G0832 SINGLE 3-INPUT POSITIVE AND-OR GATE www.ti.com SCES606C – SEPTEMBER 2004 – REVISED JANUARY 2007 DESCRIPTION/ORDERING INFORMATION (CONTINUED) By tying one input to GND or VCC, the SN74LVC1G0832 offers two more functions. When C is tied to GND, this device performs as a 2–input AND gate (Y = A • B). When A is tied to VCC, the device works as a 2–input OR gate (Y = B + C). This device also works as a 2–input OR gate when B is tied to VCC (Y = A + C).
PAGE 3
www.ti.com SN74LVC1G0832 SINGLE 3-INPUT POSITIVE AND-OR GATE SCES606C – SEPTEMBER 2004 – REVISED JANUARY 2007 LOGIC CONFIGURATIONS Figure 1. 2-Input AND Gate Figure 2. 2-Input OR Gate Figure 3.
PAGE 4
SN74LVC1G0832 SINGLE 3-INPUT POSITIVE AND-OR GATE www.ti.com SCES606C – SEPTEMBER 2004 – REVISED JANUARY 2007 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.
PAGE 5
SN74LVC1G0832 SINGLE 3-INPUT POSITIVE AND-OR GATE www.ti.com SCES606C – SEPTEMBER 2004 – REVISED JANUARY 2007 Recommended Operating Conditions VCC Supply voltage (1) Operating Data retention only High-level input voltage Low-level input voltage VO High-level output current 5.5 5.5 2 5.5 0.7 × VCC 5.5 VCC = 1.65 V to 1.95 V 0 0.35 × VCC VCC = 2.3 V to 2.7 V 0 VCC = 3 V to 3.6 V 0 VCC = 4.5 V to 5.5 V 0 VCC = 3 V to 3.6 V 0 VCC = 2.
PAGE 6
SN74LVC1G0832 SINGLE 3-INPUT POSITIVE AND-OR GATE www.ti.com SCES606C – SEPTEMBER 2004 – REVISED JANUARY 2007 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA 1.65 V to 5.5 V IOH = –4 mA IOH = –8 mA VOH VI = 5.5 V or GND IOH = –16 mA 1.9 V 2.4 2.3 4.5 V 0.1 1.65 V 0.45 2.3 V 0.3 VI = 5.5 V or GND 3.8 0.4 3V IOL = 24 mA IOL = 32 mA ICC VI = 5.
PAGE 7
SN74LVC1G0832 SINGLE 3-INPUT POSITIVE AND-OR GATE www.ti.com SCES606C – SEPTEMBER 2004 – REVISED JANUARY 2007 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.
PAGE 8
SN74LVC1G0832 SINGLE 3-INPUT POSITIVE AND-OR GATE www.ti.com SCES606C – SEPTEMBER 2004 – REVISED JANUARY 2007 PARAMETER MEASUREMENT INFORMATION (continued) VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com 14-Apr-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ SN74LVC1G0832DBVR SOT-23 3000 180.0 8.4 DBV 6 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1G0832DBVT SOT-23 DBV 6 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1G0832DCKR SC70 DCK 6 3000 180.0 8.4 2.25 2.4 1.22 4.0 8.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G0832DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0 SN74LVC1G0832DBVT SOT-23 DBV 6 250 202.0 201.0 28.0 SN74LVC1G0832DCKR SC70 DCK 6 3000 202.0 201.0 28.0 SN74LVC1G0832DCKT SC70 DCK 6 250 202.0 201.0 28.0 SN74LVC1G0832YZPR DSBGA YZP 6 3000 220.0 220.0 35.
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D: Max = 1.418 mm, Min =1.358 mm E: Max = 0.918 mm, Min =0.
PAGE 17
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.