Datasheet

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FEATURES

A C

GND

DBV PACKAGE

(TOP VIEW)

YEP OR YZP PACKAGE

(BOTTOM VIEW)

DCK PACKAGE

(TOP VIEW)

A C

GND

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION

SN74LVC1G3208

SINGLE 3-INPUT POSITIVE OR-AND GATE

SCES605A – SEPTEMBER 2004 – REVISED JUNE 2005

• Can Be Used in Three Combinations:

• Available in the Texas Instruments – OR-AND Gate

NanoStar™ and NanoFree™ Packages

– OR Gate

• Supports 5-V V

Operation

– AND Gate

• Inputs Accept Voltages to 5.5 V

• I

off

Supports Partial-Power-Down Mode

• Max t

of 5 ns at 3.3 V Operation

• Low Power Consumption, 10- µ A Max I

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ± 24-mA Output Drive at 3.3 V

• ESD Protection Exceeds JESD 22

• Input Hysteresis Allows Slow Input Transition

and Better Switching Noise Immunity at the – 2000-V Human-Body Model (A114-A)

Input

– 200-V Machine Model (A115-A)

hys

= 250 mV Typ @ 3.3 V)

– 1000-V Charged-Device Model (C101)

This device is designed for 1.65-V to 5.5-V V

operation.

The SN74LVC1G3208 is a single 3-input positive OR-AND gate. It performs the Boolean function Y = (A + B) ⋅ C

in positive logic.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

(2)

NanoStar™ – WCSP (DSBGA)

SN74LVC1G3208YEPR

0.23-mm Large Bump – YEP

Reel of 3000 _ _ _ DD _

NanoFree™ – WCSP (DSBGA)

0.23-mm Large Bump – YZP SN74LVC1G3208YZPR

(Pb-free)

–40 ° C to 85 ° C

Reel of 3000 SN74LVC1G3208DBVR

SOT (SOT-23) – DBV CDD_

Reel of 250 SN74LVC1G3208DBVT

Reel of 3000 SN74LVC1G3208DCKR

SOT (SC-70) – DCK DD_

Reel of 250 SN74LVC1G3208DCKT

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.

YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ⋅ = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoStar, NanoFree are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (17 pages)

PAGE 1
SN74LVC1G3208 SINGLE 3-INPUT POSITIVE OR-AND GATE www.ti.com SCES605A – SEPTEMBER 2004 – REVISED JUNE 2005 • FEATURES • • • • • • • Available in the Texas Instruments NanoStar™ and NanoFree™ Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 5 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typ @ 3.
PAGE 2
SN74LVC1G3208 SINGLE 3-INPUT POSITIVE OR-AND GATE www.ti.com SCES605A – SEPTEMBER 2004 – REVISED JUNE 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) By tying one input to GND or VCC, the SN74LVC1G3208 offers two more functions. When C is tied to VCC, this device performs as a 2-input OR gate (Y = A + B). When A is tied to GND, the device works as a 2-input AND gate (Y = B ⋅ C). This device also works as a 2-input AND gate when B is tied to GND (Y = A ⋅ C).
PAGE 3
SN74LVC1G3208 SINGLE 3-INPUT POSITIVE OR-AND GATE www.ti.com SCES605A – SEPTEMBER 2004 – REVISED JUNE 2005 VCC A Y A B B 1 6 2 5 3 4 Y Figure 2. 2-Input OR Gate VCC A B A Y C B 1 6 2 5 3 4 C Y Figure 3. Y = (A + B) ⋅ C Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 UNIT V VI Input voltage range (2) –0.5 6.
PAGE 4
SN74LVC1G3208 SINGLE 3-INPUT POSITIVE OR-AND GATE www.ti.com SCES605A – SEPTEMBER 2004 – REVISED JUNE 2005 Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX 1.65 5.5 1.5 Low-level input voltage V 0.65 × VCC 1.7 V 2 0.7 × VCC VCC = 1.65 V to 1.95 V VIL UNIT 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VCC = 4.
PAGE 5
SN74LVC1G3208 SINGLE 3-INPUT POSITIVE OR-AND GATE www.ti.com SCES605A – SEPTEMBER 2004 – REVISED JUNE 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH 1.65 V to 5.5 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.9 4.5 V 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 0.55 ICC VI = 5.5 V or GND IO = 0 ∆ICC One input at VCC – 0.
PAGE 6
SN74LVC1G3208 SINGLE 3-INPUT POSITIVE OR-AND GATE www.ti.com SCES605A – SEPTEMBER 2004 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.
PAGE 7
SN74LVC1G3208 SINGLE 3-INPUT POSITIVE OR-AND GATE www.ti.com SCES605A – SEPTEMBER 2004 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) SN74LVC1G3208DBVR SOT-23 DBV 6 3000 178.0 9.2 SN74LVC1G3208DBVR SOT-23 DBV 6 3000 180.0 SN74LVC1G3208DBVT SOT-23 DBV 6 250 180.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 14-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G3208DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 SN74LVC1G3208DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0 SN74LVC1G3208DBVT SOT-23 DBV 6 250 202.0 201.0 28.0 SN74LVC1G3208DBVT SOT-23 DBV 6 250 180.0 180.0 18.0 SN74LVC1G3208DCKR SC70 DCK 6 3000 180.0 180.0 18.
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D: Max = 1.418 mm, Min =1.358 mm E: Max = 0.918 mm, Min =0.
PAGE 17
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.