Datasheet

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Table Of Contents

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FEATURES

Seemechanicaldrawingsfordimensions.

DBVPACKAGE

(TOP VIEW)

GND

CLK

DCKPACKAGE

(TOP VIEW)

GND

CLK

YEP OR YZP PACKAGE

(BOTTOMVIEW)

GND

CLK

DESCRIPTION/ORDERING INFORMATION

SN74LVC1G374

SINGLE D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT

SCES520B – DECEMBER 2003 – REVISED SEPTEMBER 2006

• Available in the Texas Instruments • Latch-Up Performance Exceeds 100 mA Per

NanoStar™ and NanoFree™ Packages JESD 78, Class II

• Supports 5-V V

Operation • ESD Protection Exceeds JESD 22

• Inputs Accept Voltages to 5.5 V – 2000-V Human-Body Model (A114-A)

• Max t

of 4 ns at 3.3 V – 200-V Machine Model (A115-A)

• Low Power Consumption, 10- µ A Max I

– 1000-V Charged-Device Model (C101)

• ± 24-mA Output Drive at 3.3 V

• I

off

Supports Partial-Power-Down Mode

Operation

This single D-type latch is designed for 1.65-V to 5.5-V V

operation.

The SN74LVC1G374 features a 3-state output designed specifically for driving highly capacitive or relatively

low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O)

ports, bidirectional bus drivers, and working registers.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the

die as the package.

On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D)

input.

ORDERING INFORMATION

PACKAGE

(1)

ORDERING PART NUMBER TOP-SIDE MARKING

(2)

NanoStar – WCSP (DSBGA)

SN74LVC1G374YEPR

0.23-mm Large Bump – YEP

Reel of 3000 _ _ _D4_

NanoFree – WCSP (DSBGA)

SN74LVC1G374YZPR

0.23-mm Large Bump – YZP (Pb-free)

–40 ° C to 85 ° C

Reel of 3000 SN74LVC1G374DBVR

SOT (SOT-23) – DBV CA4_ _ _

Reel of 250 SN74LVC1G374DBVT

Reel of 3000 SN74LVC1G374DCKR

SOT (SC-70) – DCK D4_

Reel of 250 SN74LVC1G374DCKT

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.

YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition(1 = SnPb, • = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoStar, NanoFree are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (18 pages)

PAGE 1
SN74LVC1G374 SINGLE D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT www.ti.com SCES520B – DECEMBER 2003 – REVISED SEPTEMBER 2006 FEATURES • • • • • • • • Available in the Texas Instruments NanoStar™ and NanoFree™ Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.
PAGE 2
SN74LVC1G374 SINGLE D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT www.ti.com SCES520B – DECEMBER 2003 – REVISED SEPTEMBER 2006 DESCRIPTION/ORDERING INFORMATION (CONTINUED) A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly.
PAGE 3
SN74LVC1G374 SINGLE D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT www.ti.com SCES520B – DECEMBER 2003 – REVISED SEPTEMBER 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.
PAGE 4
SN74LVC1G374 SINGLE D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT www.ti.com SCES520B – DECEMBER 2003 – REVISED SEPTEMBER 2006 Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX 1.65 5.5 Low-level input voltage 0.65 × VCC 1.7 V 2 0.7 × VCC 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 V 0.3 × VCC VCC = 4.5 V to 5.
PAGE 5
SN74LVC1G374 SINGLE D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT www.ti.com SCES520B – DECEMBER 2003 – REVISED SEPTEMBER 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH 1.65 V to 5.5 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.9 4.5 V 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 (1) 3.8 0.55 4.5 V 0.55 ±1 µA ±5 µA ±10 µA 1.65 V to 5.5 V 10 µA 3 V to 5.
PAGE 6
SN74LVC1G374 SINGLE D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT www.ti.com SCES520B – DECEMBER 2003 – REVISED SEPTEMBER 2006 Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V FROM INPUT TO (OUTPUT) tpd CLK Q 2.7 18.3 1.8 8.2 1.6 6 1 4 ns ten OE Q 2 13 1.5 6.3 0.9 5 0.7 3.5 ns tdis OE Q 2 14 1.1 5.3 1.4 4.
PAGE 7
SN74LVC1G374 SINGLE D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT www.ti.com SCES520B – DECEMBER 2003 – REVISED SEPTEMBER 2006 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.
PAGE 8
SN74LVC1G374 SINGLE D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT www.ti.com SCES520B – DECEMBER 2003 – REVISED SEPTEMBER 2006 PARAMETER MEASUREMENT INFORMATION (continued) VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 13-Oct-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ SN74LVC1G374DBVR SOT-23 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DBV 6 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1G374DBVR SOT-23 DBV 6 3000 178.0 9.2 3.3 3.2 1.55 4.0 8.0 Q3 SN74LVC1G374DCKR SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 13-Oct-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G374DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0 SN74LVC1G374DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 SN74LVC1G374DCKR SC70 DCK 6 3000 180.0 180.0 18.0 SN74LVC1G374YZPR DSBGA YZP 6 3000 220.0 220.0 35.
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PAGE 17
D: Max = 1.418 mm, Min =1.358 mm E: Max = 0.918 mm, Min =0.
PAGE 18
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.