Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter XOR gate 74LVC SC 70 6

www.ti.com

FEATURES

A C

GND

DBV PACKAGE

(TOP VIEW)

YEP OR YZP PACKAGE

(BOTTOM VIEW)

DCK PACKAGE

(TOP VIEW)

A C

GND

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION

SN74LVC1G386

SINGLE 3-INPUT POSITIVE-XOR GATE

SCES439D – APRIL 2003 – REVISED JULY 2006

• Available in the Texas Instruments • Latch-Up Performance Exceeds 100 mA

NanoStar ™ and NanoFree™ Per JESD 78, Class II

Packages

• ESD Protection Exceeds JESD 22

• Supports 5-V V

Operation

– 2000-V Human-Body Model (A114-A)

• Inputs Accept Voltages to 5.5 V

– 200-V Machine Model (A115-A)

• I

off

Supports Partial-Power-Down Mode

– 1000-V Charged-Device Model (C101)

Operation

The SN74LVC1G386 performs the Boolean function Y = A ⊕ B ⊕ C in positive logic.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the

die as the package.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

(2)

NanoStar™ – WCSP (DSBGA)

SN74LVC1G386YEPR

0.23-mm Large Bump – YEP

Tape and reel _ _ _C8_

NanoFree™ – WCSP (DSBGA)

SN74LVC1G386YZPR

–40 ° C to 85 ° C

0.23-mm Large Bump – YZP (Pb-free)

SOT (SOT-23) – DBV Tape and reel SN74LVC1G386DBVR CC6_

SOT (SC-70) – DCK Tape and reel SN74LVC1G386DCKR C8_

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.

YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoStar, NanoFree are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (19 pages)

PAGE 1
SN74LVC1G386 SINGLE 3-INPUT POSITIVE-XOR GATE www.ti.com SCES439D – APRIL 2003 – REVISED JULY 2006 FEATURES • • • • • Available in the Texas Instruments NanoStar ™ and NanoFree™ Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.
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SN74LVC1G386 SINGLE 3-INPUT POSITIVE-XOR GATE www.ti.com SCES439D – APRIL 2003 – REVISED JULY 2006 FUNCTION TABLE INPUTS A B C OUTPUT Y L L L L L L H H L H L H L H H L H L L H H L H L H H L L H H H H LOGIC DIAGRAM (POSITIVE LOGIC) A B C Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.
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SN74LVC1G386 SINGLE 3-INPUT POSITIVE-XOR GATE www.ti.com SCES439D – APRIL 2003 – REVISED JULY 2006 Recommended Operating Conditions VCC Supply voltage (1) Operating Data retention only VCC = 1.65 V to 1.95 V VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX 1.65 5.5 1.5 Low-level input voltage V 0.65 × VCC 1.7 V 2 0.7 × VCC 0.35 × VCC VCC = 1.65 V to 1.95 V VIL UNIT VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 V 0.
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SN74LVC1G386 SINGLE 3-INPUT POSITIVE-XOR GATE www.ti.com SCES439D – APRIL 2003 – REVISED JULY 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH 1.65 V to 5.5 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.9 4.5 V IOL = 100 µA 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 IOL = 32 mA 0.4 ICC VI = 5.5 V or GND, IO = 0 ∆ICC One input at VCC – 0.
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SN74LVC1G386 SINGLE 3-INPUT POSITIVE-XOR GATE www.ti.com SCES439D – APRIL 2003 – REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tPZL (see Notes E and F) tPLZ (see Notes E and G) tPHZ/tPZH VLOAD VLOAD VLOAD LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.
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SN74LVC1G386 SINGLE 3-INPUT POSITIVE-XOR GATE www.ti.com SCES439D – APRIL 2003 – REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) SN74LVC1G386DBVR SOT-23 DBV 6 3000 180.0 8.4 SN74LVC1G386DCKR SC70 DCK 6 3000 180.0 SN74LVC1G386DRYR SON DRY 6 5000 180.0 SN74LVC1G386DSFR SON DSF 6 5000 SN74LVC1G386YZPR DSBGA YZP 6 3000 3.23 3.17 1.37 4.0 8.0 Q3 8.4 2.25 2.4 1.22 4.0 8.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G386DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0 SN74LVC1G386DCKR SC70 DCK 6 3000 202.0 201.0 28.0 SN74LVC1G386DRYR SON DRY 6 5000 180.0 180.0 30.0 SN74LVC1G386DSFR SON DSF 6 5000 180.0 180.0 30.0 SN74LVC1G386YZPR DSBGA YZP 6 3000 220.0 220.0 35.
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D: Max = 1.418 mm, Min =1.358 mm E: Max = 0.918 mm, Min =0.
PAGE 19
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.