Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and converter - configurable Asymmetric SOT 23 6

In1 In2

GND

In0

DBV PACKAGE

(TOP VIEW)

YZP PACKAGE

(BOTTOM VIEW)

DCK PACKAGE

(TOP VIEW)

In1 In2

GND

In0

In1 In2

GND

In0

In1

In0

In2

GND

DRL PACKAGE

(TOP VIEW)

See mechanical drawings for dimensions.

DRY PACKAGE

(TOP VIEW)

GND V

ln1

ln0

ln2

ln1

ln0

DSF PACKAGE

(TOP VIEW)

GND

ln2

SN74LVC1G57

www.ti.com

SCES414N –NOVEMBER 2002–REVISED APRIL 2013

CONFIGURABLE MULTIPLE-FUNCTION GATE

Check for Samples: SN74LVC1G57

FEATURES

• Available in the Texas Instruments NanoFree™

Operation

Package

• Latch-Up Performance Exceeds 100 mA Per

• Supports 5-V V

Operation JESD 78, Class II

• Inputs Accept Voltages to 5.5 V • ESD Protection Exceeds JESD 22

• Max t

of 6.3 ns at 3.3 V – 2000-V Human-Body Model (A114-A)

• Low Power Consumption, 10-μA Max I

– 200-V Machine Model (A115-A)

• ±24-mA Output Drive at 3.3 V – 1000-V Charged-Device Model (C101)

• I

off

Supports Partial-Power-Down Mode

DESCRIPTION

This configurable multiple-function gate is designed for 1.65-V to 5.5-V V

operation.

The SN74LVC1G57 features configurable multiple functions. The output state is determined by eight patterns of

3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter, and noninverter. All

inputs can be connected to V

or GND.

This device functions as an independent gate, but because of Schmitt action, it may have different input

threshold levels for positive-going (V

T+

) and negative-going (V

T–

) signals.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2NanoFree is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (24 pages)

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SN74LVC1G57 www.ti.com SCES414N – NOVEMBER 2002 – REVISED APRIL 2013 CONFIGURABLE MULTIPLE-FUNCTION GATE Check for Samples: SN74LVC1G57 FEATURES 1 • 2 • • • • • • Available in the Texas Instruments NanoFree™ Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 6.3 ns at 3.3 V Low Power Consumption, 10-μA Max ICC ±24-mA Output Drive at 3.
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SN74LVC1G57 SCES414N – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com Table 1. FUNCTION TABLE INPUTS OUTPUT In2 In1 In0 Y L L L H L L H L L H L H L H H L H L L L H L H L H H L H H H H H Figure 1. LOGIC DIAGRAM (POSITIVE LOGIC) In0 3 4 In1 In2 1 Y 6 Table 2. FUNCTION SELECTION TABLE LOGIC FUNCTION 2 FIGURE NO.
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SN74LVC1G57 www.ti.com SCES414N – NOVEMBER 2002 – REVISED APRIL 2013 LOGIC CONFIGURATIONS VCC A Y B A VCC A Y B A Y B 1 6 2 5 3 4 A B A Y Y B Figure 2. 2-Input AND Gate 1 6 2 5 3 4 B Y Figure 3. 2-Input NAND Gate With Inverted A Input VCC VCC A A Y B A B Y Y B A 1 6 2 5 3 4 B A Y A B Y Figure 4. 2-Input NAND Gate With Inverted B Input 1 6 2 5 3 4 B Y Figure 5. 2-Input NOR Gate VCC A Y B A 1 6 2 5 3 4 B Y Figure 6.
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SN74LVC1G57 SCES414N – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) –0.5 VCC + 0.
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SN74LVC1G57 www.ti.com SCES414N – NOVEMBER 2002 – REVISED APRIL 2013 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VT+ Positive-going input threshold voltage VT– Negative-going input threshold voltage ΔVT Hysteresis (VT+ – VT–) MIN 1.65 V 0.79 1.16 2.3 V 1.11 1.56 3V 1.5 1.87 4.5 V 2.16 2.74 VOH 5.5 V 2.61 3.33 0.35 0.62 2.3 V 0.58 0.87 3V 0.84 1.19 4.5 V 1.41 1.9 5.5 V 1.87 2.29 1.
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SN74LVC1G57 SCES414N – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7) PARAMETER tpd FROM (INPUT) TO (OUTPUT) Any In Y VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V ± 0.15 V ± 0.2 V ± 0.3 V MIN MAX 3.2 MIN MAX 14.4 2 8.3 MIN MAX 1.5 6.3 VCC = 5 V ± 0.5 V UNIT MIN MAX 1.1 5.
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SN74LVC1G57 www.ti.com SCES414N – NOVEMBER 2002 – REVISED APRIL 2013 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.
PAGE 8
SN74LVC1G57 SCES414N – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision L (January 2007) to Revision M Page • Added DRY and DSF packages to datasheet. ..................................................................................................................... 1 • Added additional package options to the ORDERING INFORMATION table. .....................................................................
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) SN74LVC1G57DBVR SOT-23 DBV 6 3000 180.0 8.4 SN74LVC1G57DCKR SC70 DCK 6 3000 180.0 SN74LVC1G57DCKR SC70 DCK 6 3000 178.0 SN74LVC1G57DRLR SOT DRL 6 4000 SN74LVC1G57DRLR SOT DRL 6 W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 9.2 2.3 2.55 1.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G57DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0 SN74LVC1G57DCKR SC70 DCK 6 3000 205.0 200.0 33.0 SN74LVC1G57DCKR SC70 DCK 6 3000 180.0 180.0 18.0 SN74LVC1G57DRLR SOT DRL 6 4000 180.0 180.0 30.0 SN74LVC1G57DRLR SOT DRL 6 4000 202.0 201.0 28.0 SN74LVC1G57DRY2 SON DRY 6 5000 180.0 180.0 30.
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D: Max = 1.418 mm, Min =1.358 mm E: Max = 0.918 mm, Min =0.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.