Datasheet

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FEATURES

Seemechanicaldrawingsfordimensions.

DBVPACKAGE

(TOP VIEW)

CLK

GND Q

DCKPACKAGE

(TOP VIEW)

CLK

GND

YZP PACKAGE

(BOTTOMVIEW)

CLK

GND

DESCRIPTION/ORDERING INFORMATION

SN74LVC1G80

SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

SCES221Q – APRIL 1999 – REVISED JANUARY 2007

• Available in the Texas Instruments • Latch-Up Performance Exceeds 100 mA Per

NanoFree™ Package JESD 78, Class II

• Supports 5-V V

Operation • ESD Protection Exceeds JESD 22

• Inputs Accept Voltages to 5.5 V – 2000-V Human-Body Model (A114-A)

• Max t

of 4.2 ns at 3.3 V – 200-V Machine Model (A115-A)

• Low Power Consumption, 10- µ A Max I

– 1000-V Charged-Device Model (C101)

• ± 24-mA Output Drive at 3.3 V

• I

off

Supports Partial-Power-Down Mode

Operation

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V V

operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the

positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the

rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without

affecting the level at the output.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

(2)

NanoFree™ – WCSP (DSBGA)

Reel of 3000 SN74LVC1G80YZPR _ _ _CX_

0.23-mm Large Bump – YZP (Pb-free)

Reel of 3000 SN74LVC1G80DBVR

SOT (SOT-23) – DBV C80_

–40°C to 85°C

Reel of 250 SN74LVC1G80DBVT

Reel of 3000 SN74LVC1G80DCKR

SOT (SC-70) – DCK CX_

Reel of 250 SN74LVC1G80DCKT

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.

YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoFree is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (18 pages)

PAGE 1
SN74LVC1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES221Q – APRIL 1999 – REVISED JANUARY 2007 FEATURES • • • • • • • • Available in the Texas Instruments NanoFree™ Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.2 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.
PAGE 2
SN74LVC1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES221Q – APRIL 1999 – REVISED JANUARY 2007 FUNCTION TABLE INPUTS OUTPUT Q CLK D ↑ H L ↑ L H L X Q0 LOGIC DIAGRAM (POSITIVE LOGIC) CLK 2 C C C 4 TG C C Q C C D 1 TG TG TG C C C Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.
PAGE 3
www.ti.com SN74LVC1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP SCES221Q – APRIL 1999 – REVISED JANUARY 2007 Recommended Operating Conditions VCC Supply voltage (1) Operating Data retention only VCC = 1.65 V to 1.95 V VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX 1.65 5.5 1.5 Low-level input voltage V 0.65 × VCC 1.7 V 2 0.7 × VCC VCC = 1.65 V to 1.95 V VIL UNIT 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.
PAGE 4
SN74LVC1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES221Q – APRIL 1999 – REVISED JANUARY 2007 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH 1.65 V to 5.5 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.9 4.5 V IOL = 100 µA 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 IOL = 32 mA CLK or D inputs 0.4 VI or VO = 5.5 V ICC VI = 5.
PAGE 5
SN74LVC1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES221Q – APRIL 1999 – REVISED JANUARY 2007 Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.
PAGE 6
SN74LVC1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES221Q – APRIL 1999 – REVISED JANUARY 2007 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.
PAGE 7
SN74LVC1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP www.ti.com SCES221Q – APRIL 1999 – REVISED JANUARY 2007 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 31-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) SN74LVC1G80DBVR SOT-23 DBV 5 3000 178.0 9.2 SN74LVC1G80DBVR SOT-23 DBV 5 3000 180.0 SN74LVC1G80DBVT SOT-23 DBV 5 250 178.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 31-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G80DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G80DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 SN74LVC1G80DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G80DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G80DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G80DCKR SC70 DCK 5 3000 205.0 200.
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D: Max = 1.418 mm, Min =1.358 mm E: Max = 0.918 mm, Min =0.
PAGE 18
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.