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DBVPACKAGE

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CLK

GND Q

DCKPACKAGE

(TOP VIEW)

CLK

GND

YZP PACKAGE

(BOTTOMVIEW)

CLK

GND

SN74LVC1G80

www.ti.com

SCES221R –APRIL 1999–REVISED DECEMBER 2013

Single Positive-Edge-Triggered D-Type Flip-Flop

Check for Samples: SN74LVC1G80

FEATURES

DESCRIPTION

This single positive-edge-triggered D-type flip-flop is

• Available in the Texas Instruments NanoFree™

designed for 1.65-V to 5.5-V V

operation.

Package

When data at the data (D) input meets the setup time

• Supports 5-V V

Operation

requirement, the data is transferred to the Q output

• Inputs Accept Voltages to 5.5 V

on the positive-going edge of the clock pulse. Clock

• Supports Down Translation to V

triggering occurs at a voltage level and is not directly

related to the rise time of the clock pulse. Following

• Max t

of 4.2 ns at 3.3 V

the hold-time interval, data at the D input can be

• Low Power Consumption, 10-µA Max I

changed without affecting the level at the output.

• ±24-mA Output Drive at 3.3 V

NanoFree™ package technology is a major

• I

off

Supports Live Insertion, Partial-Power-

breakthrough in IC packaging concepts, using the die

Down Mode, and Back-Drive Protection

as the package.

• Latch-Up Performance Exceeds 100 mA Per

This device is fully specified for partial-power-down

JESD 78, Class II

applications using I

off

. The I

off

circuitry disables the

• ESD Protection Exceeds JESD 22

outputs, preventing damaging current backflow

– 2000-V Human-Body Model (A114-A)

through the device when it is powered down.

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2NanoFree is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (19 pages)

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SN74LVC1G80 www.ti.com SCES221R – APRIL 1999 – REVISED DECEMBER 2013 Single Positive-Edge-Triggered D-Type Flip-Flop Check for Samples: SN74LVC1G80 FEATURES DESCRIPTION • This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation. 1 2 • • • • • • • • • Available in the Texas Instruments NanoFree™ Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Supports Down Translation to VCC Max tpd of 4.2 ns at 3.
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SN74LVC1G80 SCES221R – APRIL 1999 – REVISED DECEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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SN74LVC1G80 www.ti.com SCES221R – APRIL 1999 – REVISED DECEMBER 2013 Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only High-level input voltage MAX 5.5 1.5 VCC = 1.65 V to 1.95 V VIH MIN 1.65 UNIT V 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 VCC = 3 V to 3.6 V V 2 VCC = 4.5 V to 5.5 V 0.7 × VCC VCC = 1.65 V to 1.95 V 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VIL Low-level input voltage VI Input voltage 0 5.
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SN74LVC1G80 SCES221R – APRIL 1999 – REVISED DECEMBER 2013 www.ti.com Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH 1.65 V to 5.5 V MIN VCC – 0.1 1.2 1.2 IOH = –8 mA 2.3 V 1.9 1.9 2.4 2.4 2.3 2.3 3V 3.8 TYP (1) MAX 4.5 V IOL = 100 µA 1.65 V to 5.5 V 0.1 0.1 IOL = 4 mA 1.65 V 0.45 0.45 IOL = 8 mA 2.3 V 0.3 0.3 3.8 0.4 0.4 3V IOL = 32 mA VI = 5.
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SN74LVC1G80 www.ti.com SCES221R – APRIL 1999 – REVISED DECEMBER 2013 Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) SN74LVC1G80 –40°C to 85°C PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V MIN fmax VCC = 2.5 V ± 0.2 V MAX MIN 160 tpd CLK Q VCC = 3.3 V ± 0.3 V MAX 160 3 9.1 MIN VCC = 5 V ± 0.5 V MAX 160 1.5 6 1.3 MIN MAX 160 4.2 1.1 UNIT MHz 3.
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SN74LVC1G80 SCES221R – APRIL 1999 – REVISED DECEMBER 2013 www.ti.com Parameter Measurement Information VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 15 pF 15 pF 15 pF 15 pF 1 MW 1 MW 1 MW 1 MW 0.15 V 0.15 V 0.3 V 0.
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SN74LVC1G80 www.ti.com SCES221R – APRIL 1999 – REVISED DECEMBER 2013 Parameter Measurement Information VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kW 500 W 500 W 500 W 0.15 V 0.15 V 0.
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SN74LVC1G80 SCES221R – APRIL 1999 – REVISED DECEMBER 2013 www.ti.com REVISION HISTORY Changes from Revision Q (January 2007) to Revision R Page • Updated document to new TI data sheet format. ................................................................................................................. 1 • Updated Features. ................................................................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
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PACKAGE MATERIALS INFORMATION www.ti.com 7-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) SN74LVC1G80DBVR SOT-23 DBV 5 3000 180.0 8.4 3.17 1.37 4.0 8.0 Q3 SN74LVC1G80DBVR SOT-23 DBV 5 3000 178.0 9.2 SN74LVC1G80DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.55 4.0 8.0 Q3 3.23 3.17 1.37 4.0 8.0 SN74LVC1G80DBVT SOT-23 DBV 5 250 178.
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PACKAGE MATERIALS INFORMATION www.ti.com 7-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G80DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 SN74LVC1G80DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G80DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G80DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G80DCKR SC70 DCK 5 3000 205.0 200.0 33.0 SN74LVC1G80DCKR SC70 DCK 5 3000 180.0 180.
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D: Max = 1.418 mm, Min =1.358 mm E: Max = 0.918 mm, Min =0.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.