Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter XOR gate 74LVC SC 70 5

www.ti.com

FEATURES

A V

GND

DCK PACKAGE

(TOP VIEW)

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION

SN74LVC1G86-EP

SINGLE 2-INPUT EXCLUSIVE-OR GATE

SCES679 – JULY 2007

• Controlled Baseline • Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

– One Assembly/Test Site, One Fabrication

Site • ESD Protection Exceeds JESD 22

• Extended Temperature Performance of -55 ° C – 2000-V Human-Body Model (A114-A)

to 125 ° C

– 200-V Machine Model (A115-A)

• Enhanced Diminishing Manufacturing Sources

– 1000-V Charged-Device Model (C101)

(DMS) Support

• Enhanced Product-Change Notification

• Qualification Pedigree

(1)

• Supports 5-V V

Operation

• Inputs Accept Voltages to 5.5 V

• Max t

of 6.7 ns at 3.3 V

• Low Power Consumption, 15- μ A Max I

• ± 24-mA Output Drive at 3.3 V

• I

off

Supports Partial-Power-Down Mode

Operation

(1) Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over specified

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this

component beyond specified performance and environmental

limits.

This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V V

operation.

The SN74LVC1G86 performs the Boolean function Y = A ⊕ B or Y = AB + A B in positive logic.

A common application is as a true/complement element. If the input is low, the other input is reproduced in true

form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

(1)

PACKAGE

(2)

ORDERABLE PART NUMBER TOP-SIDE MARKING

(3)

–55 ° C to 125 ° C SOT (SC-70) – DCK Reel of 3000 SN74LVC1G86MDCKREP CJ_

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com .

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) DCK: The actual top-side marking has one additional character that designates the assembly/test site.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (14 pages)

PAGE 1
SN74LVC1G86-EP SINGLE 2-INPUT EXCLUSIVE-OR GATE www.ti.com SCES679 – JULY 2007 FEATURES • • • • • • • • • • • (1) Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of -55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 6.7 ns at 3.3 V Low Power Consumption, 15-μA Max ICC ±24-mA Output Drive at 3.
PAGE 2
SN74LVC1G86-EP SINGLE 2-INPUT EXCLUSIVE-OR GATE www.ti.com SCES679 – JULY 2007 FUNCTION TABLE INPUTS A B OUTPUT Y L L L L H H H L H H H L EXCLUSIVE-OR LOGIC An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. EXCLUSIVE OR =1 These are five equivalent exclusive-OR symbols valid for an SN74LVC1G86 gate in positive logic; negation may be shown at any two ports.
PAGE 3
SN74LVC1G86-EP SINGLE 2-INPUT EXCLUSIVE-OR GATE www.ti.com SCES679 – JULY 2007 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.
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SN74LVC1G86-EP SINGLE 2-INPUT EXCLUSIVE-OR GATE www.ti.com SCES679 – JULY 2007 Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX 1.65 5.5 1.5 Low-level input voltage 1.7 V 2 0.7 X VCC 0.35 X VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VCC = 4.5 V to 5.5 V V 0.3 X VCC VI Input voltage 0 5.
PAGE 5
SN74LVC1G86-EP SINGLE 2-INPUT EXCLUSIVE-OR GATE www.ti.com SCES679 – JULY 2007 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 μA VOH MIN VCC – 0.1 VCC – 0.1 1.65 V 1.2 1.2 2.3 V 1.9 1.9 2.4 2.4 2.3 2.3 3V 3.8 MAX UNIT V IOH = –32 mA 4.5 V IOL = 100 μA 1.65 V to 5.5 V 0.1 0.1 IOL = 4 mA 1.65 V 0.45 0.45 IOL = 8 mA 2.3 V 0.3 0.3 0.4 0.4 3.8 0.55 0.55 0.55 0.55 0 to 5.
PAGE 6
SN74LVC1G86-EP SINGLE 2-INPUT EXCLUSIVE-OR GATE www.ti.com SCES679 – JULY 2007 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 15 pF 15 pF 15 pF 15 pF 1 MΩ 1 MΩ 1 MΩ 1 MΩ 0.15 V 0.
PAGE 7
SN74LVC1G86-EP SINGLE 2-INPUT EXCLUSIVE-OR GATE www.ti.com SCES679 – JULY 2007 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LVC1G86MDCKREP Package Package Pins Type Drawing SC70 DCK 5 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 180.0 8.4 Pack Materials-Page 1 2.25 B0 (mm) K0 (mm) P1 (mm) 2.4 1.22 4.0 W Pin1 (mm) Quadrant 8.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G86MDCKREP SC70 DCK 5 3000 202.0 201.0 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.