Datasheet

1
FEATURES
3
2
4
61
V
CCA
V
CCB
B
GND
A
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
3
2
4
61
V
CCA
V
CCB
B
GND
A
3
2
4
61
V
CCA
V
CCB
B
GND
A
DRL PACKAGE
(TOP VIEW)
See mechanical drawings for dimensions.
DIR
DIR
DIR
5
5
5
YZP PACKAGE
(BOTTOM VIEW)
V
CCA
A
V
CCB
B
GND
1
4
2
3
6
5
DIR
C1
B1
A1
C2
B2
A2
DESCRIPTION/ORDERING INFORMATION
SN74LVC1T45
www.ti.com
..................................................................................................................................................... SCES515I DECEMBER 2003 REVISED MAY 2009
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
2
Available in the Texas Instruments NanoFree™ Max Data Rates
Package
420 Mbps (3.3-V to 5-V Translation)
Fully Configurable Dual-Rail Design Allows
210 Mbps (Translate to 3.3 V)
Each Port to Operate Over the Full 1.65-V to
140 Mbps (Translate to 2.5 V)
5.5-V Power-Supply Range
75 Mbps (Translate to 1.8 V)
V
CC
Isolation Feature If Either V
CC
Input Is at
Latch-Up Performance Exceeds 100 mA Per
GND, Both Ports Are in the High-Impedance
JESD 78, Class II
State
ESD Protection Exceeds JESD 22
DIR Input Circuit Referenced to V
CCA
2000-V Human-Body Model (A114-A)
Low Power Consumption, 4- µ A Max I
CC
200-V Machine Model (A115-A)
± 24-mA Output Drive at 3.3 V
1000-V Charged-Device Model (C101)
I
off
Supports Partial-Power-Down Mode
Operation
This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is
designed to track V
CCA
. V
CCA
accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track
V
CCB
. V
CCB
accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional
translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
The SN74LVC1T45 is designed for asynchronous communication between two data buses. The logic levels of
the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data
from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the
A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic
HIGH or LOW level applied to prevent excess I
CC
and I
CCZ
.
The SN74LVC1T45 is designed so that the DIR input is powered by V
CCA
.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The V
CC
isolation feature ensures that if either V
CC
input is at GND, then both ports are in the high-impedance
state.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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