Datasheet
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DCTPACKAGE
(TOP VIEW)
DCUPACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOMVIEW)
1
V
CC
8
1A
2
7
1B 1Y
3 6
2Y
2B
4
5
GND 2A
3 6
2B2Y
8
1
V
CC
1A
5
GND
4
2A
2
7
1Y1B
GND
5
4
2A
3 6
2B2Y
2
7
1Y1B
8
V
CC
1
1A
DESCRIPTION/ORDERING INFORMATION
SN74LVC2G132
DUAL 2-INPUT NAND GATE
WITH SCHMITT-TRIGGER INPUTS
SCES547C – FEBRUARY 2004 – REVISED JANUARY 2007
• Available in Texas Instruments NanoFree™ • I
off
Supports Partial-Power-Down Mode
Package Operation
• Supports 5-V V
CC
Operation • Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• Inputs Accept Voltages to 5.5 V
• ESD Protection Exceeds JESD 22
• Max t
pd
of 5.3 ns at 3.3 V
– 2000-V Human-Body Model (A114-A)
• Low Power Consumption, 10- µ A Max I
CC
– 200-V Machine Model (A115-A)
• ± 24-mA Output Drive at 3.3 V
– 1000-V Charged-Device Model (C101)
• Typical V
OLP
(Output Ground Bounce) <0.8 V
at V
CC
= 3.3 V, T
A
= 25 ° C
• Typical V
OHV
(Output V
OH
Undershoot) >2 V at
V
CC
= 3.3 V, T
A
= 25 ° C
This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC2G132 contains two inverters and performs the Boolean function Y = A ⋅ B or Y = A + B in positive
logic. The device functions as two independent inverters, but because of Schmitt action, it has different input
threshold levels for positive-going (V
T+
) and negative-going (V
T-
) signals.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(2)
NanoFree™ – WCSP (DSBGA)
Reel of 3000 SN74LVC2G132YZPR _ _ _D5_
0.23-mm Large Bump – YZP (Pb-free)
SSOP – DCT Reel of 3000 SN74LVC2G132DCTR C3B_ _ _
–40 ° C to 85 ° C
Reel of 3000 SN74LVC2G132DCUR
VSSOP – DCU C3B_
Reel of 250 SN74LVC2G132DCUT
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.