Datasheet

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DCUPACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOMVIEW)
1
V
CC
8
1OE
2
7
1A 2OE
3 6
2Y
1Y
4
5
GND
2A
3 6
1Y2Y
8
1
V
CC
1OE
5
GND
4
2A
2
7
2OE1A
GND
5
4
2A
3
6
1Y2Y
2
7
2OE1A
8
V
CC
1
1OE
SN74LVC2G241
www.ti.com SCES210N –APRIL 1999–REVISED NOVEMBER 2013
Dual Buffer/Driver With 3-State Outputs
Check for Samples: SN74LVC2G241
1
FEATURES
DESCRIPTION
This dual buffer/line driver is designed for 1.65-V to
2
• Available in the Texas Instruments NanoFree™
5.5-V V
CC
operation.
Package
The SN74LVC2G241 device is designed specifically
• Supports 5-V V
CC
Operation
to improve both the performance and density of 3-
• Inputs Accept Voltages to 5.5 V
state memory-address drivers, clock drivers, and bus-
• Max t
pd
of 4.1 ns at 3.3 V
oriented receivers and transmitters.
• Low Power Consumption, 10-µA Max I
CC
NanoFree™ package technology is a major
• ±24-mA Output Drive at 3.3 V
breakthrough in IC packaging concepts, using the die
as the package.
• Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25°C
The SN74LVC2G241 device is organized as two 1-bit
• Typical V
OHV
(Output V
OH
Undershoot)
line drivers with separate output-enable (1OE, 2OE)
inputs. When 1OE is low and 2OE is high, the device
>2 V at V
CC
= 3.3 V, T
A
= 25°C
passes data from the A inputs to the Y outputs. When
• I
off
Supports Live Insertion, Partial-Power-
1OE is high and 2OE is low, the outputs are in the
Down Mode, and Back-Drive Protection
high-impedance state.
• Can Be Used as a Down Translator to
To ensure the high-impedance state during power up
Translate Inputs From a Max of 5.5 V Down to
or power down, OE should be tied to V
CC
through a
the V
CC
Level
pullup resistor, and OE should be tied to GND
• Latch-Up Performance Exceeds 100 mA Per
through a pulldown resistor; the minimum value of the
JESD 78, Class II
resistor is determined by the current-sinking or the
current-sourcing capability of the driver.
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
This device is fully specified for partial-power-down
applications using I
off
. The I
off
circuitry disables the
– 200-V Machine Model (A115-A)
outputs, preventing damaging current backflow
– 1000-V Charged-Device Model (C101)
through the device when it is powered down.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.