Datasheet

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FEATURES

1A 1Y

GND

DBV PACKAGE

(TOP VIEW)

YZP PACKAGE

(BOTTOM VIEW)

DCK PACKAGE

(TOP VIEW)

1A 1Y

GND

1A 1Y

GND

DRL PACKAGE

(TOP VIEW)

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION

SN74LVC2G34

DUAL BUFFER GATE

SCES359H – AUGUST 2001 – REVISED FEBRUARY 2007

• Available in the Texas Instruments • Typical V

OHV

(Output V

Undershoot)

NanoFree™ Package >2 V at V

= 3.3 V, T

= 25 ° C

• Supports 5-V V

Operation • I

off

Supports Partial-Power-Down Mode

Operation

• Inputs Accept Voltages to 5.5 V

• Latch-Up Performance Exceeds 100 mA Per

• Max t

of 4.1 ns at 3.3 V

JESD 78, Class II

• Low Power Consumption, 10- µ A Max I

• ESD Protection Exceeds JESD 22

• ± 24-mA Output Drive at 3.3 V

– 2000-V Human-Body Model (A114-A)

• Typical V

OLP

(Output Ground Bounce)

– 200-V Machine Model (A115-A)

<0.8 V at V

= 3.3 V, T

= 25 ° C

– 1000-V Charged-Device Model (C101)

This dual buffer gate is designed for 1.65-V to 5.5-V V

operation. The SN74LVC2G34 performs the Boolean

function Y = A in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

(2)

NanoFree™ – WCSP (DSBGA)

Reel of 3000 SN74LVC2G34YZPR _ _ _C9_

0.23-mm Large Bump – YZP (Pb-free)

Reel of 3000 SN74LVC2G34DBVR

SOT (SOT-23) – DBV C34_

Reel of 250 SN74LVC2G34DBVT

–40 ° C to 85 ° C

Reel of 3000 SN74LVC2G34DCKR

SOT (SC-70) – DCK C9_

Reel of 250 SN74LVC2G34DCKT

SOT (SOT-533) – DRL Reel of 4000 SN74LVC2G34DRLR C9_

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.

YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoFree is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (17 pages)

PAGE 1
SN74LVC2G34 DUAL BUFFER GATE www.ti.com SCES359H – AUGUST 2001 – REVISED FEBRUARY 2007 FEATURES • • • • • • • • Available in the Texas Instruments NanoFree™ Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.1 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C DBV PACKAGE (TOP VIEW) 1A 1 6 • • • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.
PAGE 2
SN74LVC2G34 DUAL BUFFER GATE www.ti.com SCES359H – AUGUST 2001 – REVISED FEBRUARY 2007 FUNCTION TABLE (EACH GATE) INPUT A OUTPUT Y H H L L LOGIC DIAGRAM (POSITIVE LOGIC) 1A 2A 1 6 3 4 1Y 2Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 6.5 V range (2) VI Input voltage –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.
PAGE 3
SN74LVC2G34 DUAL BUFFER GATE www.ti.com SCES359H – AUGUST 2001 – REVISED FEBRUARY 2007 Recommended Operating Conditions VCC Supply voltage (1) Operating Data retention only VCC = 1.65 V to 1.95 V VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX 1.65 5.5 Low-level input voltage V 1.5 0.65 × VCC 1.7 V 2 0.7 × VCC 0.35 × VCC VCC = 1.65 V to 1.95 V VIL UNIT VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 V 0.3 × VCC VCC = 4.5 V to 5.
PAGE 4
SN74LVC2G34 DUAL BUFFER GATE www.ti.com SCES359H – AUGUST 2001 – REVISED FEBRUARY 2007 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH 1.65 V to 5.5 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.9 4.5 V IOL = 100 µA 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 3.8 0.4 3V IOL = 24 mA IOL = 32 mA VI = 5.5 V or GND VI or VO = 5.5 V ICC VI = 5.
PAGE 5
SN74LVC2G34 DUAL BUFFER GATE www.ti.com SCES359H – AUGUST 2001 – REVISED FEBRUARY 2007 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 28-Sep-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) SN74LVC2G34DBVR SOT-23 DBV 6 3000 180.0 9.2 3.23 1.37 4.0 8.0 Q3 SN74LVC2G34DBVR SOT-23 DBV 6 3000 178.0 9.2 SN74LVC2G34DBVR SOT-23 DBV 6 3000 178.0 9.0 3.3 3.2 1.55 4.0 8.0 Q3 3.23 3.17 1.37 4.0 8.0 SN74LVC2G34DBVT SOT-23 DBV 6 250 180.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 28-Sep-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC2G34DBVR SOT-23 DBV 6 3000 205.0 200.0 33.0 SN74LVC2G34DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 SN74LVC2G34DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 SN74LVC2G34DBVT SOT-23 DBV 6 250 205.0 200.0 33.0 SN74LVC2G34DBVT SOT-23 DBV 6 250 180.0 180.0 18.0 SN74LVC2G34DCKR SC70 DCK 6 3000 180.
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D: Max = 1.418 mm, Min =1.358 mm E: Max = 0.918 mm, Min =0.
PAGE 17
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.