Datasheet

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Seemechanicaldrawingsfordimensions.
DCTPACKAGE
(TOP VIEW)
DCUPACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOMVIEW)
1
V
CC
8
1CLK
2
7
1D 1Q
3 6
2Q
2D
4
5
GND 2CLK
3 6
2D2Q
8
1
V
CC
1CLK
5
GND
4
2CLK
2
7
1Q1D
GND
5
4
2CLK
3 6
2D2Q
2
7
1Q
1D
8
V
CC
1
1CLK
DESCRIPTION/ORDERING INFORMATION
SN74LVC2G80
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES309E – DECEMBER 2001 – REVISED FEBRUARY 2007
• Available in the Texas Instruments >2 V at V
CC
= 3.3 V, T
A
= 25°C
NanoFree™ Package
• I
off
Feature Supports Partial-Power-Down
• Supports 5-V V
CC
Operation Mode Operation
• Inputs Accept Voltages to 5.5 V • Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
• Max t
pd
of 4.2 ns at 3.3 V
• ESD Protection Exceeds JESD 22
• Low Power Consumption, 10- µ A Max I
CC
– 2000-V Human-Body Model (A114-A)
• Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25°C – 200-V Machine Model (A115-A)
• Typical V
OHV
(Output V
OH
Undershoot) – 1000-V Charged-Device Model (C101)
This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V V
CC
operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the
positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the
rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without
affecting the levels at the outputs.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(2)
NanoFree™ – WCSP (DSBGA)
Reel of 3000 SN74LVC2G80YZPR _ _ _CX_
0.23-mm Large Bump – YZP (Pb-free)
–40°C to 85°C
SSOP – DCT Reel of 3000 SN74LVC2G80DCTR C80_ _ _
VSSOP – DCU Reel of 3000 SN74LVC2G80DCUR C80_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.