Datasheet

www.ti.com
FEATURES
2B
3
2
5
81
1A V
CC
1B
GND
DCT PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
DCU PACKAGE
(TOP VIEW)
3
2
4 5
1
1A V
CC
1Y1B
GND
1B
GND
V
CC
2A
2Y
See mechanical drawings for dimensions.
2
5
3
4
8
2Y 2B
2A
2Y
1Y
2A
4
6
7
6
7
8
6
1
7
1A
2B
1Y
DESCRIPTION/ORDERING INFORMATION
SN74LVC2G86
DUAL 2-INPUT EXCLUSIVE-OR GATE
SCES360H – AUGUST 2001 – REVISED FEBRUARY 2007
• Available in the Texas Instruments • Typical V
OHV
(Output V
OH
Undershoot)
NanoFree™ Package >2 V at V
CC
= 3.3 V, T
A
= 25 ° C
• Supports 5-V V
CC
Operation • I
off
Supports Partial-Power-Down Mode
Operation
• Inputs Accept Voltages to 5.5 V
• Latch-Up Performance Exceeds 100 mA Per
• Max t
pd
of 4.7 ns at 3.3 V
JESD 78, Class II
• Low Power Consumption, 10- µ A Max I
CC
• ESD Protection Exceeds JESD 22
• ± 24-mA Output Drive at 3.3 V
– 2000-V Human-Body Model (A114-A)
• Typical V
OLP
(Output Ground Bounce)
– 200-V Machine Model (A115-A)
<0.8 V at V
CC
= 3.3 V, T
A
= 25 ° C
– 1000-V Charged-Device Model (C101)
This dual 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC2G86 performs the Boolean function Y = A ⊕ B or Y = AB + A B in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
A common application is as a true/complement element. If the input is low, the other input is reproduced in true
form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(2)
NanoFree™ – WCSP (DSBGA)
Reel of 3000 SN74LVC2G86YZPR _ _ _CH_
0.23-mm Large Bump – YZP (Pb-free)
SSOP – DCT Reel of 3000 SN74LVC2G86DCTR C86_ _ _
–40°C to 85°C
Reel of 3000 SN74LVC2G86DCUR
VSSOP – DCU C86_
Reel of 250 SN74LVC2G86DCUT
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.