Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Transducer Converter, Bidirectional, Three-state SM 8

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FEATURES

DCT OR DCU PACKAGE

(TOP VIEW)

CCA

GND

CCB

DIR

YZP PACKAGE

(BOTTOM VIEW)

GND

DIR

CCA

CCB

A1 A2

DESCRIPTION/ORDERING INFORMATION

SN74LVC2T45

DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER

WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

SCES516I – DECEMBER 2003 – REVISED MARCH 2007

• Available in the Texas Instruments

NanoFree™ Package

• Fully Configurable Dual-Rail Design Allows

Each Port to Operate Over the Full 1.65-V to

5.5-V Power-Supply Range

• V

Isolation Feature – If Either V

Input Is at

GND, Both Ports Are in the High-Impedance

State

• DIR Input Circuit Referenced to V

CCA

• Low Power Consumption, 10- µ A Max I

• ± 24-mA Output Drive at 3.3 V

• I

off

Supports Partial-Power-Down Mode

Operation

• Max Data Rates

– 420 Mbps (3.3-V to 5-V Translation)

– 210 Mbps (Translate to 3.3 V)

– 140 Mbps (Translate to 2.5 V)

– 75 Mbps (Translate to 1.8 V)

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Protection Exceeds JESD 22

– 4000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is

designed to track V

CCA

. V

CCA

accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track

CCB

. V

CCB

accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional

translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

(2)

NanoFree – WCSP (DSBGA)

Reel of 3000 SN74LVC2T45YZPR _ _ _TB_

0.23-mm Large Bump – YZP (Pb-free)

Reel of 3000 SN74LVC2T45DCTR

SSOP – DCT CT2_ _ _

–40 ° C to 85 ° C

Reel of 250 SN74LVC2T45DCTT

Reel of 3000 SN74LVC2T45DCUR

VSSOP – DCU CT2_

Reel of 250 SN74LVC2T45DCUT

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com .

(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.

DCU: The actual top-side marking has one additional character that designates the assembly/test site.

YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoFree is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

PAGE 1
SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES516I – DECEMBER 2003 – REVISED MARCH 2007 FEATURES • • • • • • • • • • Available in the Texas Instruments NanoFree™ Package Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.
PAGE 2
SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES516I – DECEMBER 2003 – REVISED MARCH 2007 DESCRIPTION/ORDERING INFORMATION (CONTINUED) The SN74LVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs.
PAGE 3
SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES516I – DECEMBER 2003 – REVISED MARCH 2007 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V A port –0.5 VCCA + 0.5 B port –0.5 VCCB + 0.
PAGE 4
SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES516I – DECEMBER 2003 – REVISED MARCH 2007 Recommended Operating Conditions (1) (2) (3) VCCI VCCA VCCB VCCO Supply voltage High-level input voltage 2.3 V to 2.7 V Data inputs (4) MAX 1.65 5.5 1.65 5.5 1.7 3 V to 3.6 V VCCI × 0.7 VCCI × 0.35 1.65 V to 1.95 V VIL Data inputs (4) 2.3 V to 2.7 V 0.7 3 V to 3.6 V 0.8 VCCA × 0.65 1.65 V to 1.
PAGE 5
SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES516I – DECEMBER 2003 – REVISED MARCH 2007 Electrical Characteristics (1) (2) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA IOH = –8 mA 1.65 V to 4.5 V 1.65 V to 4.5 V 1.65 V 1.65 V 1.2 2.3 V 2.3 V 1.9 3V 3V 2.4 3.8 VI = VIH IOH = –24 mA A port B port A or B port IOZ ICCA 0.1 1.65 V 0.45 2.
PAGE 6
SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES516I – DECEMBER 2003 – REVISED MARCH 2007 Switching Characteristics over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.
PAGE 7
SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES516I – DECEMBER 2003 – REVISED MARCH 2007 Switching Characteristics over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.
PAGE 8
SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES516I – DECEMBER 2003 – REVISED MARCH 2007 Operating Characteristics TA = 25°C PARAMETER CpdA CpdB (1) 8 (1) A-port input, B-port output B-port input, A-port output (1) A-port input, B-port output B-port input, A-port output TEST CONDITIONS CL = 0 pF, f = 10 MHz, tr = tf = 1 ns CL = 0 pF, f = 10 MHz, tr = tf = 1 ns VCCA = VCCB = 1.8 V VCCA = VCCB = 2.5 V VCCA = VCCB = 3.
PAGE 9
SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES516I – DECEMBER 2003 – REVISED MARCH 2007 Power-Up Considerations A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies. To guard against such power-up problems, take the following precautions: 1. Connect ground before any supply voltage is applied. 2. Power up VCCA. 3.
PAGE 10
SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES516I – DECEMBER 2003 – REVISED MARCH 2007 TYPICAL CHARACTERISTICS abc TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE TA = 25°C, VCCA = 1.8 V 10 10 9 9 VCCB = 1.8 V 8 8 7 7 6 6 t PLH− ns t PHL − ns VCCB = 1.8 V VCCB = 2.5 V 5 VCCB = 2.5 V 5 VCCB = 3.3 V 4 4 VCCB = 5 V VCCB = 3.
PAGE 11
SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES516I – DECEMBER 2003 – REVISED MARCH 2007 TYPICAL CHARACTERISTICS abc TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE TA = 25°C, VCCA = 2.5 V 10 10 9 9 8 8 7 VCCB = 1.8 V 6 t PLH − ns t PHL − ns 7 VCCB = 1.8 V 6 5 VCCB = 2.5 V 4 4 VCCB = 3.3 V 3 3 VCCB = 5 V 5 VCCB = 2.5 V VCCB = 3.
PAGE 12
SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES516I – DECEMBER 2003 – REVISED MARCH 2007 TYPICAL CHARACTERISTICS abc TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE TA = 25°C, VCCA = 3.3 V 10 10 9 9 8 8 7 7 VCCB = 1.8 V 6 6 t PLH − ns t PHL − ns VCCB = 1.8 V 5 VCCB = 2.5 V 4 3 VCCB = 2.5 V 5 4 VCCB = 3.3 V 3 VCCB = 5 V 2 2 VCCB = 3.
PAGE 13
SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES516I – DECEMBER 2003 – REVISED MARCH 2007 TYPICAL CHARACTERISTICS abc TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE TA = 25°C, VCCA = 5 V 10 10 9 9 8 8 7 7 VCCB = 1.8 V VCCB = 1.8 V t PLH − ns t PHL − ns 6 5 4 6 5 VCCB = 2.5 V 4 VCCB = 2.5 V VCCB = 3.3 V 3 3 2 2 VCCB = 5 V VCCB = 3.
PAGE 14
SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES516I – DECEMBER 2003 – REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION 2 × VCCO S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCCO GND RL tw LOAD CIRCUIT VCCI VCCI/2 Input VCCO CL RL VTP 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V 15 pF 15 pF 15 pF 15 pF 2 kΩ 2 kΩ 2 kΩ 2 kΩ 0.15 V 0.15 V 0.3 V 0.
PAGE 15
SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES516I – DECEMBER 2003 – REVISED MARCH 2007 APPLICATION INFORMATION The following shows an example of the SN74LVC2T45 being used in a unidirectional logic level-shifting application. VCC1 VCC2 VCC1 VCC2 1 8 2 7 3 6 4 5 VCC2 VCC1 SYSTEM-1 SYSTEM-2 PIN NAME FUNCTION 1 VCCA VCC1 SYSTEM-1 supply voltage (1.65 V to 5.
PAGE 16
SN74LVC2T45 DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS www.ti.com SCES516I – DECEMBER 2003 – REVISED MARCH 2007 APPLICATION INFORMATION Figure 3 shows the SN74LVC2T45 being used in a bidirectional logic level-shifting application. Since the SN74LVC2T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
PAGE 17
PACKAGE OPTION ADDENDUM www.ti.
PAGE 18
PACKAGE OPTION ADDENDUM www.ti.com 17-Nov-2013 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 27-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVC2T45DCUR US8 DCU 8 3000 180.0 9.0 2.05 3.3 1.0 4.0 8.0 Q3 SN74LVC2T45DCUR US8 DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3 SN74LVC2T45DCURG4 US8 DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.
PAGE 20
PACKAGE MATERIALS INFORMATION www.ti.com 27-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC2T45DCUR US8 DCU 8 3000 182.0 182.0 20.0 SN74LVC2T45DCUR US8 DCU 8 3000 202.0 201.0 28.0 SN74LVC2T45DCURG4 US8 DCU 8 3000 202.0 201.0 28.0 SN74LVC2T45DCUTG4 US8 DCU 8 250 202.0 201.0 28.0 SN74LVC2T45YZPR DSBGA YZP 8 3000 220.0 220.0 35.0 SN74LVC2T45YZPR DSBGA YZP 8 3000 182.0 182.0 17.
PAGE 21
MECHANICAL DATA MPDS049B – MAY 1999 – REVISED OCTOBER 2002 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 8 0,13 M 5 0,15 NOM ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 2,90 2,70 4,25 3,75 Gage Plane PIN 1 INDEX AREA 1 0,25 4 0° – 8° 3,15 2,75 0,60 0,20 1,30 MAX Seating Plane 0,10 0,10 0,00 NOTES: A. B. C. D. 4188781/C 09/02 All linear dimensions are in millimeters. This drawing is subject to change without notice.
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D: Max = 1.918 mm, Min =1.858 mm E: Max = 0.918 mm, Min =0.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.