Datasheet

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FEATURES

DB, DW, OR PW PACKAGE

(TOP VIEW)

LEBA

OEBA

CEAB

GND

CEBA

LEAB

OEAB

DESCRIPTION/ORDERING INFORMATION

SN74LVC543A

OCTAL REGISTERED TRANSCEIVER

WITH 3-STATE OUTPUTS

SCAS299H – JANUARY 1993 – REVISED MARCH 2005

• Operates From 1.65 V to 3.6 V

• Inputs Accept Voltages to 5.5 V

• Max t

of 7 ns at 3.3 V

• Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25 ° C

• Typical V

OHV

(Output V

Undershoot)

>2 V at V

= 3.3 V, T

= 25 ° C

• Supports Mixed-Mode Signal Operation on All

Ports (5-V Input/Output Voltage With

3.3-V V

)

• I

off

Supports Partial-Power-Down Mode

Operation

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

This octal registered transceiver is designed for 1.65-V to 3.6-V V

operation.

The SN74LVC543A contains two sets of D-type latches for temporary storage of data flowing in either direction.

Separate latch-enable ( LEAB or LEBA) and output-enable ( OEAB or OEBA) inputs are provided for each register

to permit independent control in either direction of data flow.

The A-to-B enable ( CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and

LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB places the A

latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the

data present at the output of the A latches. Data flow for B to A is similar to that of A to B, but uses CEBA, LEBA,

and OEBA.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

Tube of 25 SN74LVC543ADW

SOIC – DW LVC543A

Reel of 2000 SN74LVC543ADWR

SSOP – DB Reel of 2000 SN74LVC543ADBR LC543A

–40 ° C to 85 ° C

Tube of 60 SN74LVC543APW

TSSOP – PW Reel of 2000 SN74LVC543APWR LC543A

Reel of 250 SN74LVC543APWT

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (16 pages)

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SN74LVC543A OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS299H – JANUARY 1993 – REVISED MARCH 2005 FEATURES • • • • • • • • DB, DW, OR PW PACKAGE (TOP VIEW) Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 7 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.
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SN74LVC543A OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS299H – JANUARY 1993 – REVISED MARCH 2005 FUNCTION TABLE (1) INPUTS (1) (2) CEAB LEAB OEAB A OUTPUT B H X X X Z X X H X Z L H L X B0 (2) L L L L L L L L H H A-to-B data flow is shown; B-to-A flow control is the same, except that it uses CEBA, LEBA, and OEBA.
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SN74LVC543A OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com Absolute Maximum Ratings SCAS299H – JANUARY 1993 – REVISED MARCH 2005 (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.
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SN74LVC543A OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS299H – JANUARY 1993 – REVISED MARCH 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH 1.65 V to 3.6 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = –24 mA 3V 2.2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.7 IOL = 12 mA 2.7 V 0.4 3V 0.
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SN74LVC543A OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS299H – JANUARY 1993 – REVISED MARCH 2005 Operating Characteristics TA = 25°C PARAMETER Cpd (1) Power dissipation capacitance Outputs enabled per transceiver Outputs disabled TEST CONDITIONS f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP (1) (1) 49 (1) (1) 6 UNIT pF This information was not available at the time of publication.
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SN74LVC543A OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS299H – JANUARY 1993 – REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LVC543ADBR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 SN74LVC543ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 SN74LVC543APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC543ADBR SSOP DB 24 2000 367.0 367.0 38.0 SN74LVC543ADWR SOIC DW 24 2000 367.0 367.0 45.0 SN74LVC543APWR TSSOP PW 24 2000 367.0 367.0 38.0 SN74LVC543APWT TSSOP PW 24 250 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.