Datasheet

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FEATURES

SN74LVC573A . . . RGY PACKAGE

(TOP VIEW)

1 20

10 11

GND

SN54LVC573A . . . J OR W PACKAGE

SN74LVC573A . . . DB, DGV, DW, N,

NS, OR PW PACKAGE

(TOP VIEW)

GND

SN54LVC573A . . . FK PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

7Q 1Q

GND

DESCRIPTION/ORDERING INFORMATION

SN54LVC573A, SN74LVC573A

OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCAS300R – JANUARY 1993 – REVISED SEPTEMBER 2005

• Operate From 1.65 V to 3.6 V • I

off

Supports Partial-Power-Down Mode

Operation

• Inputs Accept Voltages to 5.5 V

• Latch-Up Performance Exceeds 250 mA Per

• Max t

of 6.9 ns at 3.3 V

JESD 17

• Typical V

OLP

(Output Ground Bounce) <0.8 V

• ESD Protection Exceeds JESD 22

at V

= 3.3 V, T

= 25 ° C

– 2000-V Human-Body Model (A114-A)

• Typical V

OHV

(Output V

Undershoot) >2 V at

= 3.3 V, T

= 25 ° C – 200-V Machine Model (A115-A)

• Support Mixed-Mode Signal Operation on All – 1000-V Charged-Device Model (C101)

Ports (5-V Input/Output Voltage With 3.3-V xxxxx

)

The SN54LVC573A octal transparent D-type latch is designed for 2.7-V to 3.6-V V

operation, and the

SN74LVC573A octal transparent D-type latch is designed for 1.65-V to 3.6-V V

operation.

These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively

low-impedance loads. They are particularly suitable for implementing buffer registers, input/output (I/O) ports,

bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q

outputs are latched at the logic levels at the D inputs.

A buffered output-enable ( OE) input can be used to place the eight outputs in either a normal logic state (high or

low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the

bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

These devices are fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the

outputs, preventing damaging current backflow through the device when it is powered down.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

On products compliant to MIL-PRF-38535, all parameters are

Instruments standard warranty. Production processing does not

tested unless otherwise noted. On all other products, production

necessarily include testing of all parameters.

processing does not necessarily include testing of all parameters.

Summary of content (29 pages)

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SN54LVC573A, SN74LVC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCAS300R – JANUARY 1993 – REVISED SEPTEMBER 2005 FEATURES 1 20 2 19 3 18 4 5 17 16 6 7 15 14 8 9 13 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE xxxxx 1D 2D 3D 4D 5D 6D 7D 8D 20 19 1Q 18 2Q 3 17 3Q 16 4Q 4 5 7 15 5Q 14 6Q 8 13 7Q 6 12 8Q 9 10 11 3D 4D 5D 6D 7D 1Q 1 2 SN54LVC573A . . . FK PACKAGE (TOP VIEW) 2D 1D OE VCC SN74LVC573A . . .
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SN54LVC573A, SN74LVC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCAS300R – JANUARY 1993 – REVISED SEPTEMBER 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices.
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SN54LVC573A, SN74LVC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCAS300R – JANUARY 1993 – REVISED SEPTEMBER 2005 LOGIC DIAGRAM (POSITIVE LOGIC) OE LE 1 11 C1 1D 2 19 1D 1Q To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages. Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage –0.5 6.5 V VI Input voltage range (2) –0.5 6.
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SN54LVC573A, SN74LVC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCAS300R – JANUARY 1993 – REVISED SEPTEMBER 2005 Recommended Operating Conditions (1) SN54LVC573A VCC Supply voltage VIH High-level input voltage Operating Data retention only MIN MAX MIN MAX 2 3.6 1.65 3.6 1.5 1.5 VCC = 2.3 V to 2.7 V 1.7 2 Low-level input voltage Input voltage VO Output voltage 0.7 0.8 High-level output current 0 5.5 0 5.
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SN54LVC573A, SN74LVC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCAS300R – JANUARY 1993 – REVISED SEPTEMBER 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 2.7 V to 3.6 V 1.2 2.3 V 1.7 2.2 2.2 3V 2.4 2.4 3V 2.2 2.2 0.2 2.7 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.7 IOL = 12 mA 2.7 V 0.4 0.4 IOL = 24 mA 3V 0.55 0.55 ±5 ±5 µA 3.
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SN54LVC573A, SN74LVC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCAS300R – JANUARY 1993 – REVISED SEPTEMBER 2005 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN74LVC573A VCC = 1.8 V ± 0.15 V MIN MAX VCC = 2.5 V ± 0.2 V MIN VCC = 3.3 V ± 0.3 V VCC = 2.7 V MAX MIN MAX MIN UNIT MAX tw Pulse duration, LE high 9 4 3.3 3.
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SN54LVC573A, SN74LVC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCAS300R – JANUARY 1993 – REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.5 2.5 12.0 16.0 Q1 SN74LVC573ADBR SSOP DB 20 2000 330.0 16.4 SN74LVC573ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC573ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC573ADBR SSOP DB 20 2000 367.0 367.0 38.0 SN74LVC573ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74LVC573ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LVC573ANSR SO NS 20 2000 367.0 367.0 45.0 SN74LVC573APWR TSSOP PW 20 2000 364.0 364.0 27.0 SN74LVC573APWT TSSOP PW 20 250 367.0 367.0 38.
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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