Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Standard Three-state, Non-inverting TSSOP 20

SN54LVC574A, SN74LVC574A

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCAS301R − JANUARY 1993 − REVISED MARCH 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Operate From 1.65 V to 3.6 V

D Inputs Accept Voltages to 5.5 V

D Specified From −40°C to 85°C,

−40°C to 125°C, and −55°C to 125°C

D Max t

of 7 ns at 3.3 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2 V at V

= 3.3 V, T

= 25°C

D Support Mixed-Mode Signal Operation on

All Ports (5-V Input/Output Voltage With

3.3-V V

)

D I

off

Supports Partial-Power-Down Mode

Operation

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

SN54LVC574A ...J OR W PACKAGE

SN74LVC574A . . . DB, DGV, DW, N, NS,

OR PW PACKAGE

(TOP VIEW)

SN54LVC574A . . . FK PACKAGE

(TOP VIEW)

GND

CLK

3212019

910111213

7Q 1Q

GND

CLK

SN74LVC574A . . . RGY PACKAGE

(TOP VIEW)

120

10 11

CLK

GND

description/ordering information

The SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V V

operation, and the

SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V

operation.

These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively

low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional

bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.

A buffered output-enable (OE

) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus

lines without interface or pullup components.

does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

These devices are fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the

outputs, preventing damaging current backflow through the device when it is powered down.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Summary of content (32 pages)

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SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK All Ports (5-V Input/Output Voltage With 3.
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SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices.
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SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 logic diagram (positive logic) OE CLK 1 11 C1 1D 2 19 1Q 1D To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 recommended operating conditions (see Note 7) SN54LVC574A −55 TO 125°C MIN MAX 2 3.6 Operating VCC Supply voltage VIH High-level input voltage VCC = 2.7 V to 3.6 V VIL Low-level input voltage VCC = 2.7 V to 3.
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SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LVC574A PARAMETER TEST CONDITIONS VCC −55 TO 125°C MIN IOH = −100 μA VOH 2.7 V to 3.6 V 2.2 3V 2.4 3V 2.2 IOH = −24 mA IOL = 100 μA VOL ‡ MAX V 2.7 V to 3.6 V 0.2 IOL = 12 mA 2.7 V 0.4 IOL = 24 mA 3V 0.55 V II VI = 5.5 V or GND 3.
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SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN74LVC574A PARAMETER TEST CONDITIONS TA = 25°C VCC MIN IOH = −100 μA VOH 1.65 V to 3.6 V MAX MIN VCC − 0.2 VCC − 0.2 1.29 1.2 1.2 IOH = −8 mA 2.3 V 1.9 1.7 1.7 2.7 V 2.2 2.2 2.2 3V 2.4 2.4 2.4 3V 2.3 IOL = 100 μA 2.2 V 2.2 0.1 0.2 0.
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SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVC574A PARAMETER FROM (INPUT) TO (OUTPUT) −55 TO 125°C VCC MIN fmax 2.7 V 150 3.3 V ± 0.3 V 150 CLK Q ten OE Q tdis OE Q MAX MHz 8 2.7 V tpd UNIT 3.3 V ± 0.3 V 1 7 1 7.5 0.5 6.4 ns 9 2.7 V 3.3 V ± 0.3 V 7 2.7 V 3.3 V ± 0.
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SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN74LVC574A PARAMETER FROM (INPUT) TO (OUTPUT) TA = 25°C VCC MIN 1.8 V ± 0.15 V fmax tpd CLK ten OE tdis OE Q Q Q TYP −40 TO 85°C MAX 55 MIN MAX 55 MIN UNIT MAX 40 2.5 V ± 02 V 95 95 80 2.7 V 150 150 150 3.3 V ± 0.
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SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION VLOAD RL From Output Under Test CL (see Note A) S1 Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL VΔ VCC/2 VCC/2 1.5 V 1.
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SN54LVC574A, SN74LVC574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS301R − JANUARY 1993 − REVISED MARCH 2005 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 8.2 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.5 2.5 12.0 16.0 Q1 SN74LVC574ADBR SSOP DB 20 2000 330.0 16.4 SN74LVC574ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC574ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC574ADBR SSOP DB 20 2000 367.0 367.0 38.0 SN74LVC574ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74LVC574ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LVC574ANSR SO NS 20 2000 367.0 367.0 45.0 SN74LVC574APWR TSSOP PW 20 2000 364.0 364.0 27.0 SN74LVC574APWR TSSOP PW 20 2000 367.0 367.0 38.
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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