Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Receiver, transceiver TSSOP 24

www.ti.com

FEATURES

SN54LVC652A . . . JT OR W PACKAGE

SN74LVC652A . . . DB, DW, NS, OR PW PACKAGE

(TOP VIEW)

CLKAB

SAB

OEAB

GND

CLKBA

SBA

OEBA

SN54LVC652A . . . FK PACKAGE

(TOP VIEW)

3 2 1 28 27

12 13

OEBA

4 26

14 15 16 17 18

GND

OEAB

SAB

CLKAB

CLKBA

SBA

NC - No internal connection

DESCRIPTION/ORDERING INFORMATION

SN54LVC652A, SN74LVC652A

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCAS303L – JANUARY 1993 – REVISED SEPTEMBER 2005

• Operate From 1.65 V to 3.6 V • Support Mixed-Mode Signal Operation on All

Ports (5-V Input/Output Voltage With 3.3-V

• Inputs Accept Voltages to 5.5 V

)

• Max t

of 7.4 ns at 3.3 V

• I

off

Supports Partial-Power-Down Mode

• Typical V

OLP

(Output Ground Bounce) <0.8 V

Operation

at V

= 3.3 V, T

= 25 ° C

• ESD Protection Exceeds JESD 22

• Typical V

OHV

(Output V

Undershoot) >2 V at

– 2000-V Human-Body Model (A114-A)

= 3.3 V, T

= 25 ° C

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

The SN54LVC652A octal bus transceiver and register is designed for 2.7-V to 3.6-V V

operation, and the

SN74LVC652A octal bus transceiver and register is designed for 1.65-V to 3.6-V V

operation.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

Tube of 25 SN74LVC652ADW

SOIC – DW LVC652A

Reel of 2000 SN74LVC652ADWR

SOP – NS Reel of 2000 SN74LVC652ANSR LVC652A

–40 ° C to 85 ° C SSOP – DB Reel of 2000 SN74LVC652ADBR LC652A

Tube of 60 SN74LVC652APW

TSSOP – PW Reel of 2000 SN74LVC652APWR LC652A

Reel of 250 SN74LVC652APWT

CDIP – JT Tube of 15 SNJ54LVC652AJT SNJ54LVC652AJT

–55 ° C to 125 ° C CFP – W Tube of 85 SNJ54LVC652AW SNJ54LVC652AW

LCCC – FK Tube of 42 SNJ54LVC652AFK SNJ54LVC652AFK

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

On products compliant to MIL-PRF-38535, all parameters are

Instruments standard warranty. Production processing does not

tested unless otherwise noted. On all other products, production

necessarily include testing of all parameters.

processing does not necessarily include testing of all parameters.

Summary of content (23 pages)

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SN54LVC652A, SN74LVC652A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS www.ti.com SCAS303L – JANUARY 1993 – REVISED SEPTEMBER 2005 FEATURES • Operate From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 7.4 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C • • • Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.
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SN54LVC652A, SN74LVC652A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS www.ti.com SCAS303L – JANUARY 1993 – REVISED SEPTEMBER 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions.
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SN54LVC652A, SN74LVC652A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS www.ti.
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SN54LVC652A, SN74LVC652A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS www.ti.com SCAS303L – JANUARY 1993 – REVISED SEPTEMBER 2005 LOGIC DIAGRAM (POSITIVE LOGIC) OEBA OEAB CLKBA SBA CLKAB SAB 21 3 23 22 1 2 One of Eight Channels 1D C1 A1 4 20 1D C1 To Seven Other Channels Pin numbers shown are for the DB, DW, JT, NS, PW, and W packages.
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SN54LVC652A, SN74LVC652A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS www.ti.com SCAS303L – JANUARY 1993 – REVISED SEPTEMBER 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.
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SN54LVC652A, SN74LVC652A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS www.ti.com SCAS303L – JANUARY 1993 – REVISED SEPTEMBER 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 2.7 V to 3.6 V 1.2 1.7 2.7 V 2.2 2.2 3V 2.4 2.4 3V 2.2 2.2 V 1.65 V to 3.6 V 0.2 2.7 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.7 IOL = 12 mA 2.7 V 0.4 0.4 IOL = 24 mA 3V 0.55 0.
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SN54LVC652A, SN74LVC652A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS www.ti.com SCAS303L – JANUARY 1993 – REVISED SEPTEMBER 2005 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) SN74LVC652A VCC = 1.8 V ± 0.15 V MIN VCC = 2.5 V ± 0.2 V MAX MIN MAX (1) VCC = 2.7 V MIN MAX (1) VCC = 3.3 V ± 0.3 V MIN MAX fclock Clock frequency tw Pulse duration (1) (1) 3.3 3.3 ns tsu Setup time, data before CLK↑ (1) (1) 1.
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SN54LVC652A, SN74LVC652A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS www.ti.com SCAS303L – JANUARY 1993 – REVISED SEPTEMBER 2005 Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER Cpd (1) 8 Power dissipation capacitance per transceiver Outputs enabled Outputs disabled f = 10 MHz This information was not available at the time of publication. VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP (1) (1) 84 (1) (1) 9.
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SN54LVC652A, SN74LVC652A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS www.ti.com SCAS303L – JANUARY 1993 – REVISED SEPTEMBER 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 25-Sep-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVC652ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 SN74LVC652APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 SN74LVC652APWT TSSOP PW 24 250 330.0 16.4 6.95 8.3 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC652ADWR SOIC DW 24 2000 367.0 367.0 45.0 SN74LVC652APWR TSSOP PW 24 2000 367.0 367.0 38.0 SN74LVC652APWT TSSOP PW 24 250 367.0 367.0 38.
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MECHANICAL DATA MCER004A – JANUARY 1995 – REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN PINS ** A 13 24 B 1 24 28 A MAX 1.280 (32,51) 1.460 (37,08) A MIN 1.240 (31,50) 1.440 (36,58) B MAX 0.300 (7,62) 0.291 (7,39) B MIN 0.245 (6,22) 0.285 (7,24) DIM 12 0.070 (1,78) 0.030 (0,76) 0.100 (2,54) MAX 0.320 (8,13) 0.290 (7,37) 0.015 (0,38) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.014 (0,36) 0.008 (0,20) 0.
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MECHANICAL DATA MCFP007 – OCTOBER 1994 W (R-GDFP-F24) CERAMIC DUAL FLATPACK 0.375 (9,53) 0.340 (8,64) Base and Seating Plane 0.006 (0,15) 0.004 (0,10) 0.090 (2,29) 0.045 (1,14) 0.045 (1,14) 0.026 (0,66) 0.395 (10,03) 0.360 (9,14) 0.360 (9,14) 0.240 (6,10) 1 0.360 (9,14) 0.240 (6,10) 24 0.019 (0,48) 0.015 (0,38) 0.050 (1,27) 0.640 (16,26) 0.490 (12,45) 0.030 (0,76) 0.015 (0,38) 12 13 30° TYP 1.115 (28,32) 0.840 (21,34) 4040180-5 / B 03/95 NOTES: A. B. C. D. E.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.