Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Standard Three-state, Non-inverting TSSOP 24

www.ti.com

FEATURES

DB, DGV, DW, NS, OR PW PACKAGE

(TOP VIEW)

10D

GND

10Q

CLK

DESCRIPTION/ORDERING INFORMATION

SN74LVC821A

10-BIT BUS-INTERFACE FLIP-FLOP

WITH 3-STATE OUTPUTS

SCAS304J – MARCH 1993 – REVISED FEBRUARY 2005

• Operates From 1.65 V to 3.6 V

• Inputs Accept Voltages to 5.5 V

• Max t

of 7.3 ns at 3.3 V

• Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25 ° C

• Typical V

OHV

(Output V

Undershoot)

>2 V at V

= 3.3 V, T

= 25 ° C

• Supports Mixed-Mode Signal Operation on All

Ports (5-V Input/Output Voltage With

3.3-V V

)

• I

off

Supports Partial-Power-Down Mode

Operation

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

This 10-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V V

operation.

The SN74LVC821A features 3-state outputs designed specifically for driving highly capacitive or relatively

low-impedance loads. This device is particularly suitable for implementing wider buffer registers, I/O ports,

bidirectional bus drivers with parity, and working registers.

The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the

device provides true data at the Q outputs.

A buffered output-enable ( OE) input can be used to place the ten outputs in either a normal logic state (high or

low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the

bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without interface or pullup components.

OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can

be entered while the outputs are in the high-impedance state.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

Tube of 25 SN74LVC821ADW

SOIC – DW LVC821A

Reel of 2000 SN74LVC821ADWR

SOP – NS Reel of 2000 SN74LVC821ANSR LVC821A

SSOP – DB Reel of 2000 SN74LVC821ADBR LC821A

–40 ° C to 85 ° C

Tube of 60 SN74LVC821APW

TSSOP – PW Reel of 2000 SN74LVC821APWR LC821A

Reel of 250 SN74LVC821APWT

TVSOP – DGV Reel of 2000 SN74LVC821ADGVR LC821A

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (17 pages)

PAGE 1
SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS304J – MARCH 1993 – REVISED FEBRUARY 2005 FEATURES • • • • • • • • • DB, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 7.3 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.
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SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS304J – MARCH 1993 – REVISED FEBRUARY 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff.
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SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com Absolute Maximum Ratings SCAS304J – MARCH 1993 – REVISED FEBRUARY 2005 (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.
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SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS304J – MARCH 1993 – REVISED FEBRUARY 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH IOH = –4 mA 1.65 V 1.2 IOH = –8 mA 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = –24 mA 3V 2.2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.7 IOL = 12 mA 2.7 V 0.4 3V 0.
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SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS304J – MARCH 1993 – REVISED FEBRUARY 2005 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V MIN VCC = 2.5 V ± 0.2 V MAX MIN MAX MIN MAX VCC = 3.3 V ± 0.3 V MIN (1) tpd CLK Q (1) (1) (1) (1) 8.5 2.2 7.3 ns ten OE Q (1) (1) (1) (1) 8.8 1.3 7.6 ns Q (1) (1) (1) (1) 6.
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SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS304J – MARCH 1993 – REVISED FEBRUARY 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.8 2.5 12.0 16.0 Q1 SN74LVC821ADBR SSOP DB 24 2000 330.0 16.4 SN74LVC821ADGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC821ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC821ADBR SSOP DB 24 2000 367.0 367.0 38.0 SN74LVC821ADGVR TVSOP DGV 24 2000 367.0 367.0 35.0 SN74LVC821ADWR SOIC DW 24 2000 367.0 367.0 45.0 SN74LVC821APWR TSSOP PW 24 2000 367.0 367.0 38.0 SN74LVC821APWT TSSOP PW 24 250 367.0 367.0 38.
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.