Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver SSOP 24

www.ti.com

FEATURES

DB, DGV, DW, NS, OR PW PACKAGE

(TOP VIEW)

OE1

A10

GND

Y10

OE2

DESCRIPTION/ORDERING INFORMATION

SN74LVC827A

10-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

SCAS306J – MARCH 1993 – REVISED FEBRUARY 2005

• Operates From 1.65 V to 3.6 V

• Inputs Accept Voltages to 5.5 V

• Max t

of 6.7 ns at 3.3 V

• Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25 ° C

• Typical V

OHV

(Output V

Undershoot)

>2 V at V

= 3.3 V, T

= 25 ° C

• Supports Mixed-Mode Signal Operation on All

Ports (5-V Input/Output Voltage With

3.3-V V

)

• I

off

Supports Partial-Power-Down Mode

Operation

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

This 10-bit buffer/bus driver is designed for 1.65-V to 3.6-V V

operation.

The SN74LVC827A provides a high-performance bus interface for wide data paths or buses carrying parity.

The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable ( OE1 or OE2)

input is high, all ten outputs are in the high-impedance state. The SN74LVC827A provides true data at its

outputs.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in

a mixed 3.3-V/5-V system environment.

To ensure the high-impedance state during power up or power down, OE should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

Tube of 25 SN74LVC827ADW

SOIC – DW LVC827A

Reel of 2000 SN74LVC827ADWR

SOP – NS Reel of 2000 SN74LVC827ANSR LVC827A

SSOP – DB Reel of 2000 SN74LVC827ADBR LC827A

–40 ° C to 85 ° C

Tube of 60 SN74LVC827APW

TSSOP – PW Reel of 2000 SN74LVC827APWR LC827A

Reel of 250 SN74LVC827APWT

TVSOP – DGV Reel of 2000 SN74LVC827ADGVR LC827A

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (16 pages)

PAGE 1
SN74LVC827A 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS306J – MARCH 1993 – REVISED FEBRUARY 2005 FEATURES • • • • • • • • • DB, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 6.7 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.
PAGE 2
SN74LVC827A 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.
PAGE 3
SN74LVC827A 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com Absolute Maximum Ratings SCAS306J – MARCH 1993 – REVISED FEBRUARY 2005 (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.
PAGE 4
SN74LVC827A 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS306J – MARCH 1993 – REVISED FEBRUARY 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH IOH = –4 mA 1.65 V 1.2 IOH = –8 mA 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = –24 mA 3V 2.2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.7 IOL = 12 mA 2.7 V 0.4 3V 0.55 IOL = 24 mA VI or VO = 5.
PAGE 5
SN74LVC827A 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS306J – MARCH 1993 – REVISED FEBRUARY 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.8 2.5 12.0 16.0 Q1 SN74LVC827ADBR SSOP DB 24 2000 330.0 16.4 SN74LVC827ADGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC827ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC827ADBR SSOP DB 24 2000 367.0 367.0 38.0 SN74LVC827ADGVR TVSOP DGV 24 2000 367.0 367.0 35.0 SN74LVC827ADWR SOIC DW 24 2000 367.0 367.0 45.0 SN74LVC827APWR TSSOP PW 24 2000 367.0 367.0 38.0 SN74LVC827APWT TSSOP PW 24 250 367.0 367.0 38.
PAGE 10
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 11
PAGE 12
PAGE 13
PAGE 14
PAGE 15
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 16
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.