Datasheet

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FEATURES
SN54LVCH244A . . . J OR W PACKAGE
SN74LVCH244A . . . DB, DBQ, DGV, DW,
NS, OR PW PACKAGE
(TOP VIEW)
SN54LVCH244A . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
1Y1
2A4
1Y2
2A3
1Y3
1A2
2Y3
1A3
2Y2
1A4
2Y4
1A1
1OE
1Y4
2A2 2OE
2Y1
GND
2A1
V
CC
SN74LVCH244A . . . RGY PACKAGE
(TOP VIEW)
1 20
10 11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
1OE
2A1
V
GND
CC
DESCRIPTION/ORDERING INFORMATION
SN54LVCH244A , , SN74LVCH244A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES009O JULY 1995 REVISED FEBRUARY 2007
Operate From 1.65 V to 3.6 V I
off
Supports Partial-Power-Down Mode
Operation
Inputs Accept Voltages to 5.5 V
Bus Hold on Data Inputs Eliminates the Need
Max t
pd
of 5.9 ns at 3.3 V
for External Pullup/Pulldown Resistors
Typical V
OLP
(Output Ground Bounce)
Latch-Up Performance Exceeds 250 mA Per
<0.8 V at V
CC
= 3.3 V, T
A
= 25 ° C
JESD 17
Typical V
OHV
(Output V
OH
Undershoot)
ESD Protection Exceeds JESD 22
>2 V at V
CC
= 3.3 V, T
A
= 25 ° C
2000-V Human-Body Model (A114-A)
Support Mixed-Mode Signal Operation on All
Ports 200-V Machine Model (A115-A)
(5-V Input/Output Voltage With 3.3-V V
CC
)
1000-V Charged-Device Model (C101)
The SN54LVCH244A octal buffer/line driver is designed for 2.7-V to 3.6-V V
CC
operation, and the
SN74LVCH244A octal buffer/line driver is designed for 1.65-V to 3.6-V V
CC
operation.
These devices are organized as two 4-bit line drivers with separate output-enable ( OE) inputs. When OE is low,
these devices pass data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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