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FEATURES

DESCRIPTION/ORDERING INFORMATION

DGG OR DL PACKAGE

(TOP VIEW)

1DIR

1B1

1B2

GND

1B3

1B4

1B5

1B6

GND

1B7

1B8

2B1

2B2

GND

2B3

2B4

2B5

2B6

GND

2B7

2B8

2DIR

1OE

1A1

1A2

GND

1A3

1A4

1A5

1A6

GND

1A7

1A8

2A1

2A2

GND

2A3

2A4

2A5

2A6

GND

2A7

2A8

2OE

This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the

SN74LVCR162245

16-BIT BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES047E – AUGUST 1995 – REVISED MARCH 2005

• Member of the Texas Instruments Widebus™

Family

• Operates From 2.7 V to 3.6 V

• Inputs Accept Voltages to 5.5 V

• Max t

of 8.5 ns at 3.3 V

• Typical V

OLP

(Output Ground Bounce) < 0.8 V

at V

= 3.3 V, T

= 25 ° C

• Typical V

OHV

(Output V

Undershoot) > 2 V at

= 3.3 V, T

= 25 ° C

• Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

• All Outputs Have Equivalent 26- Ω Series

Resistors, So No External Resistors Are

Required

• Latch-Up Performance Exceeds 250 mA Per

JEDEC Standard JESD-17

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

This 16-bit (dual-octal) noninverting bus transceiver is

designed for 2.7-V to 3.6-V V

operation.

The SN74LVCR162245 is designed for asynchronous

communication between data buses. The

control-function implementation minimizes external

timing requirements.

A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR)

input. The output-enable ( OE) input can be used to disable the device so that the buses effectively are isolated.

All outputs, which are designed to sink up to 12 mA, include 26- Ω resistors to reduce overshoot and undershoot.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or

pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input

circuit and is not disabled by OE or DIR.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

Tube SN74LVCR162245DL

SSOP – DL LVCR162245

Tape and reel SN74LVCR162245DLR

–40 ° C to 85 ° C TSSOP – DGG Tape and reel SN74LVCR162245DGGR LVCR162245

VFBGA – GQL SN74LVCR162245KR

Tape and reel LEP245

VFBGA – ZQL (Pb-free) 74LVCR162245ZQLR

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (15 pages)

PAGE 1
SN74LVCR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES047E – AUGUST 1995 – REVISED MARCH 2005 FEATURES • • • • • • • • • • DGG OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus™ Family Operates From 2.7 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 8.5 ns at 3.3 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.
PAGE 2
SN74LVCR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES047E – AUGUST 1995 – REVISED MARCH 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
PAGE 3
SN74LVCR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES047E – AUGUST 1995 – REVISED MARCH 2005 LOGIC DIAGRAM (POSITIVE LOGIC) 1DIR 1 48 1A1 1OE 47 2 1B1 To Seven Other Channels 2DIR 24 25 2A1 2OE 36 13 2B1 Pin numbers shown are for the DGG and DL packages.
PAGE 4
SN74LVCR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES047E – AUGUST 1995 – REVISED MARCH 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX –0.5 4.6 Except I/O ports (2) –0.5 VCC + 4.6 I/O ports (2) (3) –0.5 VCC + 0.5 –0.5 VCC + 0.
PAGE 5
SN74LVCR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES047E – AUGUST 1995 – REVISED MARCH 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VCC (1) TEST CONDITIONS IOH = –100 µA VOH MIN to MAX IOH = –4 mA, VIH = 2 V IOH = –8 mA, VIH = 2 V IOH = –6 mA, VIH = 2 V IOH = –12 mA, VIH = 2 V Il VIL = 0.8 V IOL = 8 mA, VIL = 0.8 V IOL = 6 mA, VIL = 0.8 V IOL = 12 mA, VIL = 0.8 V 0.4 0.6 V 0.55 0.
PAGE 6
SN74LVCR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES047E – AUGUST 1995 – REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 500 Ω 2.7 V LOAD CIRCUIT FOR OUTPUTS 1.5 V Timing Input 0V tw tsu 2.7 V Input 1.5 V 2.7 V 1.5 V 0V 1.5 V Data Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V 1.5 V 0V tPLH 1.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 10-Oct-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device 74LVCR162245ZQLR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant BGA MI CROSTA R JUNI OR ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 SN74LVCR162245DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 10-Oct-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74LVCR162245ZQLR BGA MICROSTAR JUNIOR ZQL 56 1000 333.2 345.9 28.6 SN74LVCR162245DGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74LVCR162245DLR SSOP DL 48 1000 367.0 367.0 55.
PAGE 11
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PAGE 14
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 15
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.