Datasheet

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www.ti.com

FEATURES

D OR PW PACKAGE

(TOP VIEW)

1OE

2OE

GND

4OE

3OE

DESCRIPTION/ORDERING INFORMATION

SN74LVT125-EP

3.3-V ABT QUADRUPLE BUS BUFFER

WITH 3-STATE OUTPUTS

SCBS796A – JANUARY 2004 – REVISED JUNE 2005

• Supports Unregulated Battery Operation

Down to 2.7 V

• Controlled Baseline

• Typical V

OLP

(Output Ground Bounce) < 0.8 V

– One Assembly/Test Site, One Fabrication

at V

= 3.3 V, T

= 25 ° C

Site

• I

off

Supports Partial-Power-Down Mode

• Extended Temperature Performance of

Operation

–40 ° C to 125 ° C

• Bus-Hold Data Inputs Eliminate the Need for

• Enhanced Diminishing Manufacturing

External Pullup Resistors

Sources (DMS) Support

• Enhanced Product-Change Notification

• Qualification Pedigree

(1)

• ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

• Supports Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V V

)

(1)

Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

This bus buffer is designed specifically for low-voltage (3.3-V) V

operation, but with the capability to provide a

TTL interface to a 5-V system environment.

The SN74LVT125 features independent line drivers with 3-state outputs. Each output is in the high-impedance

state when the associated output-enable ( OE) input is high.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

SOIC – D Tape and reel SN74LVT125QDREP LVT125E

–40 ° C to 125 ° C

TSSOP – PW Tape and reel SN74LVT125QPWREP LVT125E

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (11 pages)

PAGE 1
SN74LVT125-EP 3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS www.ti.
PAGE 2
SN74LVT125-EP 3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS www.ti.com SCBS796A – JANUARY 2004 – REVISED JUNE 2005 FUNCTION TABLE (EACH BUFFER) INPUTS OE A OUTPUT Y L H H L L L H X Z LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1A 2OE 2A 3OE 3A 4OE 4A 1 2 3 1Y 4 5 6 2Y 10 9 8 3Y 13 12 11 4Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.
PAGE 3
SN74LVT125-EP 3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS www.ti.com SCBS796A – JANUARY 2004 – REVISED JUNE 2005 Recommended Operating Conditions (1) MIN MAX 2.7 3.6 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage 5.5 V IOH High-level output current –32 mA IOL Low-level output current 32 mA ∆t/∆v Input transition rise or fall rate 10 ns/V TA Operating free-air temperature 125 °C (1) V 2 V 0.
PAGE 4
SN74LVT125-EP 3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS www.ti.com SCBS796A – JANUARY 2004 – REVISED JUNE 2005 Switching Characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ (1) 4 FROM (INPUT) TO (OUTPUT) A Y OE Y OE Y All typical values are at VCC = 3.3 V, TA = 25°C. VCC = 3.3 V ± 0.3 V MIN VCC = 2.7 V TYP (1) MAX UNIT MIN MAX 1 2.7 4.2 4.7 1 2.9 4.1 5.1 1 3.
PAGE 5
SN74LVT125-EP 3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS www.ti.com SCBS796A – JANUARY 2004 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 500 Ω 2.7 V LOAD CIRCUIT FOR OUTPUTS 1.5 V Timing Input 0V tw tsu 2.7 V 1.5 V Input th 2.7 V 1.5 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVT125QPWREP ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04705-01XE ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 7
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LVT125QPWREP Package Package Pins Type Drawing TSSOP PW 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVT125QPWREP TSSOP PW 14 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.